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參數(shù)資料
| 型號(hào)： | ADV7343BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER VIDEO W/DAC 64-LQFP |
| 產(chǎn)品變化通告： | ADV734x, ADV739x Feature Improvement |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | DVD，Blu-Ray |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7342/ADV7343
Data Sheet
Rev. D | Page 4 of 108
REVISION HISTORY
3/12—Rev. C to Rev. D
Changed ADV7340/ADV7341 to ADV7342/ADV7343........... 70
3/12—Rev. B to Rev. C
Reorganized Layout............................................................Universal
Change to Features Section ............................................................. 1
Moved Revision History Section .................................................... 4
Change to Table 1 ............................................................................. 5
Changes to Digital Input/Output Specifications—
1.8 V Section ..................................................................................... 8
Changes to Table 15........................................................................ 21
Changes to Table 21........................................................................ 33
Changes to Table 24........................................................................ 36
Changes to Table 29........................................................................ 41
Changes to Table 30........................................................................ 42
Changes to 24-Bit 4:4:4 RGB Mode Section ............................... 48
Deleted ED/HD Nonstandard Timing Mode Section, Figure 59,
and Table 42, Renumbered Sequentially ..................................... 50
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode
Section, and Figure 60.................................................................... 51
Deleted Figure 61............................................................................ 52
Added External Sync Polarity Section ......................................... 52
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section .................................................................................... 53
Changes to ED/HD Test Patterns Section ................................... 81
9/11—Rev. A to Rev. B
Changes to MPU Port Description Section ................................ 27
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Deleted Detailed Features Section, Changes to Table 1............... 4
Changes to Figure 1.......................................................................... 5
Changes to Table 6............................................................................ 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 7 ................................................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................ 8
Added Table 9.................................................................................... 9
Changes to MPU Port Timing Specifications Section,
Default Conditions ......................................................................... 10
Deleted Figure 20............................................................................ 18
Changes to Table 13........................................................................ 19
Changes to Table 15 ....................................................................... 20
Changes to MPU Port Description Section ................................ 27
Changes to I2C Operation Section ............................................... 27
Added Table 16 ............................................................................... 27
Added Figure 49 ............................................................................. 28
Changes to Table 17 ....................................................................... 29
Changes to Table 18 ....................................................................... 29
Changes to Table 21, 0x30 Bit Description ................................. 32
Changes to Table 29 ....................................................................... 39
Changes to Table 30 ....................................................................... 40
Changes to Table 31, 0xA0 Register Name ................................. 42
Changes to Table 32 ....................................................................... 43
Added Table 33 and Table 34 ........................................................ 44
Changes to Standard Definition Only Section ........................... 46
Added Figure 52 ............................................................................. 47
Changes to Figure 53...................................................................... 47
Changes to Figure 56, Figure 57, and Figure 58 ......................... 48
Renamed Features Section to Design Features Section............. 50
Changes to ED/HD Nonstandard Timing Mode Section......... 50
Changes to Figure 60...................................................................... 51
Added HD Interlace External P_HSYNC and P_VSYNC
Considerations Section.................................................................. 51
Changes to SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section .................................................. 51
Changes to Programming the FSC Section................................... 53
Changes to Subaddress 0x8C to Subaddress 0x8F Section ....... 53
Changes to Subaddress 0x82, Bit 4 Section................................. 53
Added SD Manual CSC Matrix Adjust Feature Section............ 56
Changes to Subaddress 0x9C to Subaddress 0x9F Section ....... 57
Changes to SD Brightness Detect Section................................... 58
Changes to Figure 71...................................................................... 60
Added Sleep Mode Section ........................................................... 68
Changes to Pixel and Control Port Readback Section .............. 68
Added SD Teletext Insertion Section........................................... 68
Added Unused Pins Section.......................................................... 70
Added Figure 86 and Figure 87 .................................................... 70
Changes to Power Supply Sequencing Section........................... 72
Changes to Figure 94...................................................................... 75
Changes to SD Wide Screen Signaling Section .......................... 77
Changes to Internal Test Pattern Generation Section ............... 79
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section.................................. 80
Added Configuration Scripts Section.......................................... 92
10/06—Revision 0: Initial Version
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADV7343WBSTZ | 功能描述:IC ENCODER VID 12BIT DAC 64LQFP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1 |
| ADV7343WBSTZ-RL | 功能描述:Video Encoder IC DVD, Blu-Ray 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1,500 |
| ADV7344 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| ADV7344BSTZ | 制造商:Analog Devices 功能描述: |
| ADV73505501 | 制造商:LG Corporation 功能描述:Frame Assembly |
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