
Data Sheet
ADV7342/ADV7343
Rev. | Page 11 of 108
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
Conditions
Min
Typ
Max
Unit
SCL Frequency
0
400
kHz
SCL High Pulse Width, t1
0.6
s
SCL Low Pulse Width, t2
1.3
s
Hold Time (Start Condition), t3
0.6
s
Setup Time (Start Condition), t4
0.6
s
Data Setup Time, t5
100
ns
SDA, SCL Rise Time, t6
300
ns
SDA, SCL Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
s
1
Guaranteed by characterization.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
Conditions
Min
Typ
Max
Unit
SD only (16× oversampling)
90
mA
ED only (8× oversamplin
g)465
mA
HD only (4× oversampling
)491
mA
SD (16× oversampling) and ED (8× oversampling)
95
mA
SD (16× oversampling) and HD (4× oversampling)
122
mA
IDD_IO
1
mA
Three DACs enabled (ED/HD only)
124
mA
Six DACs enabled (SD only and simultaneous modes )
140
mA
IPLL
SD only, ED only, or HD only modes
5
mA
Simultaneous modes
10
mA
SLEEP MODE
IDD
5
A
IAA
0.3
A
IDD_IO
0.2
A
IPLL
0.1
A
1
RSET1 = 510 (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 k (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
2
75% color bar test pattern applied to pixel data pins.
3
IDD is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
IAA is the total current required to supply all DACs.
D