參數(shù)資料
型號： ADV7343BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 23/108頁
文件大小： 0K
描述： IC ENCODER VIDEO W/DAC 64-LQFP
產(chǎn)品變化通告： ADV734x, ADV739x Feature Improvement
標準包裝： 1
類型： 視頻編碼器
應用： DVD，Blu-Ray
電壓 - 電源，模擬： 3.3V
電壓 - 電源，數(shù)字： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
Data Sheet
ADV7342/ADV7343
Rev. | Page 21 of 108
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
G
ND_I
O
63
CL
KI
N_B
62
S7
61
S6
60
S5
59
S4
58
S3
57
DG
ND
56
V
DD
55
S2
54
S1
53
S0
52
T
EST
5
51
T
EST
4
50
S
_HS
Y
NC
49
S_
VSYN
C
47
RSET1
46
VREF
45
COMP1
42
DAC 3
43
DAC 2
44
DAC 1
48
SFL
41
VAA
40
AGND
39
DAC 4
37
DAC 6
36
RSET2
35
COMP2
34
PVDD
33
EXT_LF1
38
DAC 5
2
TEST0
3
TEST1
4
Y0
7
Y3
6
Y2
5
Y1
1
VDD_IO
8
Y4
9
Y5
10
VDD
12
Y6
13
Y7
14
TEST2
15
TEST3
16
C0
11
DGND
17
C1
18
C2
19
AL
S
B
20
S
DA
21
S
CL
22 23
P
_HS
Y
NC
24
P_
VSYN
C
25
P
_BL
ANK
26
C4
C3
27
C5
28
C6
29
C7
30
CL
KI
N_A
31 32
P
G
ND
PIN 1
ADV7342/ADV7343
TOP VIEW
(Not to Scale)
E
X
T_
LF2
06399-
021
Figure 20. Pin Configuration
Table 15. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Description
13, 12,
9 to 4
Y7 to Y0
I
8-Bit Pixel Port. Y0 is the LSB. Refer to Table 36 for input modes.
29 to 25,
18 to 16
C7 to C0
I
8-Bit Pixel Port. C0 is the LSB. Refer to Table 36 for input modes.
62 to 58,
55 to 53
S7 to S0
I
8-Bit Pixel Port. S0 is the LSB. Refer to Table 36 for input modes.
52, 51, 15,
14, 3, 2
TEST5 to
TEST0
I
Unused. These pins should be connected to DGND.
30
CLKIN_A
I
Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz), or SD Only (27 MHz).
63
CLKIN_B
I
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
50
S_HSYNC
I/O
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
49
S_VSYNC
I/O
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
22
P_HSYNC
I
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
23
P_VSYNC
I
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
24
P_BLANK
I
48
SFL
I/O
Subcarrier Frequency Lock (SFL) Input. The SFL input is used to drive the color subcarrier DDS
system.
47
RSET1
I
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 load), a 510 resistor must be connected from RSET1 to
AGND. For low-drive operation (for example, into a 300 load), a 4.12 k resistor must be
connected from RSET1 to AGND.
D
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