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參數(shù)資料
| 型號： | ADV7192 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| 中文描述： | 視頻編碼器與六10位DAC，54兆赫采樣和逐行掃描輸入 |
| 文件頁數(shù)： | 50/69頁 |
| 文件大小： | 664K |
| 代理商： | ADV7192 |
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ADV7192
–50–
REV. 0
Time, t
PD
,
is the time needed by the ADV7192 to interpolate
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears t
SYNTXTOUT
= 10.2
μ
s after the leading edge
of the horizontal signal. Time TXT
DEL
is the pipeline delay time
by the source that is gated by the TTREQ signal in order to de-
liver TTX data.
With the programmability that is offered with TTXREQ signal
on the Rising/Falling edges, the TTX data is always inserted at
the correct position of 10.2
μ
s after the leading edge of Horizontal
Sync pulse, thus this enables a source interface with variable
pipeline delays.
The width of the TTXREQ signal must always be maintained
such that it allows the insertion of 360 (in order to comply with
the Teletext Standard PAL-WST) teletext bits at a text data rate
of 6.9375 Mbits/s, this is achieved by setting TC03
–
TC00 to 0.
The insertion window is not open if the Teletext Enable bit
(MR34) is set to 0.
APPENDIX 5
TELETEXT INSERTION
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is given as follows:
(27
MHz
/4) = 6.75
MHz
(6.9375
×
10
6
/6.75
×
10
6
= 1.027777
Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit
has a width of almost four clock cycles. The ADV7192 uses an
internal sequencer and variable phase interpolation
fi
lter to mini-
mize the phase jitter and thus generate a bandlimited signal
which can be output on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that
TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are Bits 47, 56, 65, and 74. This scheme
holds for all following cycles of 37 TTX bits, until all 360 TTX
bits are completed. All teletext lines are implemented in the
same way. Individual control of teletext lines are controlled
by Teletext Setup Registers.
ADDRESS & DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
Figure 99. Teletext VBI Line
PROGRAMMABLE PULSE EDGES
t
PD
t
PD
CVBS/Y
HSYNC
TTXREQ
TTX
DATA
t
SYNTXTOUT
= 10.2 s
t
TTX
DEL
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
t
SYNTXTOUT
10.2 s
TTX
DEL
TTX
ST
Figure 100. Teletext Functionality Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7194KST | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194 | Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7202 | Simultaneous Sampling Video Rate Codec |
| ADV7300A | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
| ADV7300AKST | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7192KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| ADV7194 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling |
| ADV7194KST | 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7194KSTZ | 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
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