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參數(shù)資料
| 型號(hào)： | ADV7192 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| 中文描述： | 視頻編碼器與六10位DAC，54兆赫采樣和逐行掃描輸入 |
| 文件頁數(shù)： | 19/69頁 |
| 文件大?。?/td> | 664K |
| 代理商： | ADV7192 |
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ADV7192
–
19
–
REV. 0
27MHz
54MHz
6
D
A
C
O
U
T
P
U
T
S
ENCODER
ADV7192
MPEG2
PLL
ENCODER
CORE
PIXEL BUS
I
N
T
E
R
P
O
L
A
T
I
O
N
2
PROGRESSIVE
SCAN
DECODER
30-BIT INTERFACE
Figure 34. Block Diagram Using the ADV7192 in Progres-
sive Scan Mode
The progressive scan decoder deinterlaces the data from the
MPEG2 decoder. This now means that there are 525 video lines
per field in NTSC mode and 625 video lines per field in PAL
mode. The duration of the video line is now 32
μ
s.
It is important to note that the data from the MPEG2 decoder
is in 4:2:2 format. The data output from the progressive scan
decoder is in 4:4:4 format. Thus it is assumed that some form of
interpolation on the color component data is performed in the
progressive scan decoder IC. (Mode Register 8.)
REAL-TIME CONTROL, SUBCARRIER RESET, AND
TIMING RESET
Together with the SCRESET/RTC/TR pin and Mode Register 4
(Genlock Control), the ADV7192 can be used in (a) Timing
Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode.
(a) A TIMING RESET is achieved in holding this pin high. In
this state the horizontal and vertical counters will remain reset.
On releasing this pin (set to low), the internal counters will
commence counting again. The minimum time the pin has
to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise
the reset signal might not be recognized.
(b) The SUBCARRIER PHASE will reset to that of Field 0 at
the start of the following field when a low to high transition
occurs on this input pin.
(c) In RTC MODE, the ADV7192 can be used to lock to an ex-
ternal video source.
The real-time control mode allows the ADV7192 to auto-
matically alter the subcarrier frequency to compensate for line
length variations. When the part is connected to a device
that outputs a digital datastream in the RTC format (such as
a ADV7185 video decoder, see Figure 38), the part will
automatically change to the compensated subcarrier frequency
on a line-by-line basis. This digital datastream is 67 bits
wide and the subcarrier is contained in Bits 0 to 21. Each bit
is two clock cycles long. 00Hex should be written into all four
Subcarrier Frequency registers when using this mode. (Mode
Register 4.)
SCH PHASE MODE
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor SCH
phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7192 is configured in RTC
mode. Under these conditions (unstable video) the Subcarrier
Phase Reset should be enabled but no reset applied. In this
configuration the SCH Phase will never be reset; this means that
the output video will now track the unstable input video. The Sub-
carrier Phase Reset when applied will reset the SCH phase to Field
0 at the start of the next field (e.g., Subcarrier Phase Reset applied
in Field 5 (PAL) on the start of the next field SCH phase will be
reset to Field 0). (Mode Register 4.)
SLEEP MODE
If, after
RESET
, the SCRESET/RTC/TR and NTSC_PAL pins
are both set high, the ADV7192 will power up in Sleep Mode to
facilitate low power consumption before all registers have been
initialized.
If Power-up in Sleep Mode is disabled, Sleep Mode control
passes to the Sleep Mode control in Mode Register 2 (i.e., con-
trol via I
2
C). (Mode Register 2 and Mode Register 6.)
SQUARE PIXEL MODE
The ADV7192 can be used to operate in square pixel mode. For
NTSC operation an input clock of 24.5454 MHz is required.
Alternatively, for PAL operation, an input clock of 29.5 MHz
is required. The internal timing logic adjusts accordingly for
square pixel mode operation. Square pixel mode is not available
in 4
×
Oversampling mode. (Mode Register 2.)
VERTICAL BLANKING DATA INSERTION AND
BLANK
INPUT
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not have line sync or pre-/post-equal-
ization pulses . This mode of operation is called
Partial Blanking
. It
allows the insertion of any VBI data (Opened VBI) into the
encoded output waveform, this data is present in digitized
incoming YCbCr data stream (e.g., WSS data, CGMS, VPS
etc.). Alternatively the entire VBI may be blanked (no VBI data
inserted) on these lines. VBI is available in all timing modes.
The complete VBI is comprised of the following lines:
525/60 systems, Lines 525 to 21 for field one and Lines 262 to
Line 284 for field two.
625/50 systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:
525/60 systems, Lines 10 to 21 for field one and second half of
Line 273 to Line 284 for field two.
625/50 systems, Lines 7 to 22 and Lines 319 to 335.
(Mode Register 3.)
It is possible to allow control over the
BLANK
signal using
Timing Register 0. When the
BLANK
input is enabled (TR03 =
0 and input pin tied low), the
BLANK
input can be used to
input externally generated blank signals in Slave Mode 1, 2, or
3. When the
BLANK
input is disabled (TR03 = 1 and input pin
tied low or tied high) the
BLANK
input is not used and the
ADV7192 automatically blanks all normally blank lines as per
CCIR-624. (Timing Register 0.)
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| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
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