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ADV7192
–29–
REV. 0
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7192 with the exception of the Subaddress Registers which
are write only registers. The Subaddress Register determines
which register the next read or write operation accesses. All com-
munications with the part through the bus start with an access
to the Subaddress Register. Then a read/write operation is per-
formed from/to the target address which then increments to
the next address until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register. All registers can
be read from as well as written to.
ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
SR6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
SR5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
SR4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
SR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
SR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
SR1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
SR0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
MODE REGISTER 5
MODE REGISTER 6
MODE REGISTER 7
MODE REGISTER 8
MODE REGISTER 9
TIMING REGISTER 0
TIMING REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
CLOSED CAPTIONING EXTENDED DATA BYTE 0
CLOSED CAPTIONING EXTENDED DATA BYTE 1
CLOSED CAPTIONING DATA BYTE 0
CLOSED CAPTIONING DATA BYTE 1
NTSC PEDESTAL/TELETEXT CONTROL REGISTER 0
NTSC PEDESTAL/TELETEXT CONTROL REGISTER 1
NTSC PEDESTAL/TELETEXT CONTROL REGISTER 2
NTSC PEDESTAL/TELETEXT CONTROL REGISTER 3
CGMS/WSS 0
CGMS/WSS 1
CGMS/WSS 2
TELETEXT REQUEST CONTROL REGISTER
CONTRAST CONTROL REGISTER
U SCALE REGISTER
V SCALE REGISTER
HUE ADJUST CONTROL REGISTER
BRIGHTNESS CONTROL REGISTER
SHARPNESS RESPONSE REGISTER
DNR REGISTER 0
DNR REGISTER 1
DNR REGISTER 2
GAMMA CORRECTION REGISTER 0
GAMMA CORRECTION REGISTER 1
GAMMA CORRECTION REGISTER 2
GAMMA CORRECTION REGISTER 3
GAMMA CORRECTION REGISTER 4
GAMMA CORRECTION REGISTER 5
GAMMA CORRECTION REGISTER 6
GAMMA CORRECTION REGISTER 7
GAMMA CORRECTION REGISTER 8
GAMMA CORRECTION REGISTER 9
GAMMA CORRECTION REGISTER 10
GAMMA CORRECTION REGISTER 11
GAMMA CORRECTION REGISTER 12
GAMMA CORRECTION REGISTER 13
BRIGHTNESS DETECT REGISTER
OUTPUT CLOCK REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
MACROVISION REGISTER
ADV7192 SUBADDRESS REGISTER
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR7
ZERO SHOULD
BE WRITTEN
HERE
Figure 55. Subaddress Register for the ADV7192
Subaddress Register (SR7–SR0)
The Communications Register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation takes
place.
Figure 55 shows the various operations under the control of the
Subaddress Register 0 should always be written to SR7.
Register Select (SR6–SR0)
These bits are set up to point to the required starting address.