參數(shù)資料
型號(hào)： ADV7192
廠商： Analog Devices, Inc.
英文描述： Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
中文描述： 視頻編碼器與六10位DAC，54兆赫采樣和逐行掃描輸入
文件頁(yè)數(shù)： 18/69頁(yè)
文件大?。?/td> 664K
代理商： ADV7192
ADV7192
–
18
–
REV. 0
UNDERSHOOT LIMITER
A limiter is placed after the digital filters. This prevents any
synchronization problems for TVs. The level of undershoot is
programmable between –1.5 IRE, –6 IRE, –11 IRE when oper-
ating in 4
×
Oversampling Mode. In 2
×
Oversampling Mode the
limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing
Register 0.)
DIGITAL NOISE REDUCTION
DNR is applied to the Y data only. A filter block selects the
high frequency, low amplitude components of the incoming
signal (DNR Input Select). The absolute value of the filter output
is compared to a programmable threshold value (DNR Thresh-
old Control). There are two DNR modes available: DNR Mode
and DNR Sharpness Mode.
In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (Coring Gain Control) of this noise signal will be sub-
tracted from the original signal.
In DNR Sharpness Mode, if the absolute value of the filter output
is less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (Coring
Gain Control) will be added to the original signal in order to boost
high frequency components and to sharpen the video image.
In MPEG systems it is common to process the video information
in blocks of 8
×
8 pixels for MPEG2 systems, or 16
×
16 pixels
for MPEG1 systems ('Block Size Control'). DNR can be applied
to the resulting block transition areas that are known to contain
noise. Generally the block transition area contains two pixels. It
is possible to define this area to contain four pixels (Border Area
Control).
It is also possible to compensate for variable block positioning or
differences in YCrCb pixel timing with the use of the Block Offset
Control. (Mode Register 8, DNR Registers 0–2.)
DOUBLE BUFFERING
Double buffering can be enabled or disabled on the following
registers: Closed Captioning Registers, Brightness Control Reg-
ister, V-Scale, U-Scale Contrast Control Register, Hue Adjust
Register, Macrovision Registers, and the Gamma Curve Select
bit. These registers are updated once per field on the falling
edge of the
VSYNC
signal. Double Buffering improves the overall
performance of the ADV7192, since modifications to register
settings will not be made during active video, but take effect on
the start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROL
Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if
gamma correction is enabled. Gamma correction allows the
mapping of the luma data to a user-defined function. (Mode
Register 8, Gamma Correction Registers 0–13.)
NTSC PEDESTAL CONTROL
In NTSC mode it is possible to have the pedestal signal gener-
ated on the output video signal. (Mode Register 2.)
POWER-ON
RESET
After power-up, it is necessary to execute a
RESET
operation. A
reset occurs on the falling edge of a high-to-low transition on the
RESET
pin. This initializes the pixel port such that the data on
the pixel inputs pins is ignored. See Appendix 8 for the register
settings after
RESET
is applied.
PROGRESSIVE SCAN INPUT
It is possible to input data to the ADV7192 in progressive scan
format. For this purpose the input pins Y0/P8–Y7/P15, Y8–Y9,
Cr0–Cr9 and Cb0–Cb9 accept 10-bit Y data, 10-bit Cb data
and 10-bit Cr data. The data is clocked into the part at 27 MHz.
The data is then filtered and sinc corrected in an 2 Interpo-
lation filter and then output to three video DACs at 54 MHz
(to interface to a progressive scan monitor).
FREQUENCY
–
MHz
0
0
30
5
A
–
10
15
20
25
–
10
–
20
–
30
–
50
–
60
–
40
–
70
Figure 32. Plot of the Interpolation Filter for the Y Data
FREQUENCY
–
MHz
0
0
30
5
A
–
10
15
20
25
–
10
–
20
–
30
–
50
–
60
–
40
–
70
Figure 33. Plot of the Interpolation Filter for the CrCb Data
It is assumed that there is no color space conversion or any other
such operation to be performed on the incoming data. Thus if
these DAC outputs are to drive a TV, all relevant timing and
synchronization data should be contained in the incoming digital
Y
data.
The block diagram below shows a possible configuration for
progressive scan mode using the ADV7192.
相關(guān)PDF資料
PDF描述
ADV7194KST Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
ADV7194 Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
ADV7202 Simultaneous Sampling Video Rate Codec
ADV7300A Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
ADV7300AKST Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV⑩ 12-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7192KST 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7194 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
ADV7194KST 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7194KSTZ 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7194KSTZ 制造商:Analog Devices 功能描述:TV / Video IC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*