參數(shù)資料
型號(hào): ADV7192
廠商: Analog Devices, Inc.
英文描述: Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
中文描述: 視頻編碼器與六10位DAC,54兆赫采樣和逐行掃描輸入
文件頁(yè)數(shù): 22/69頁(yè)
文件大?。?/td> 664K
代理商: ADV7192
ADV7192
22
REV. 0
Mode 0 (CCIR–656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7192 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing
information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before and after each line
during active picture and retrace. Mode 0 is illustrated in Figure 39. The
HSYNC
,
VSYNC
and
BLANK
(if not used) pins should be
tied high during this mode. Blank output is available.
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
bYC
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
268 CLOCK
4 CLOCK
4 CLOCK
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
Figure 39. Timing Mode 0, Slave Mode
Mode 0 (CCIR–656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7192 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video)
Time Codes in the CCIR656 standard. The H bit is output on the
HSYNC
pin, the V bit is output on the
BLANK
pin and the
F bit is output on the
VSYNC
pin. Mode 0 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). The H, V, and F transitions relative
to the video waveform are illustrated in Figure 42.
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
H
V
F
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
H
V
F
DISPLAY
Figure 40. Timing Mode 0, NTSC Master Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ADV7194KSTZ 制造商:Analog Devices 功能描述:TV / Video IC