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參數(shù)資料
| 型號(hào)： | ADV7192 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs |
| 中文描述： | 視頻編碼器與六10位DAC，54兆赫采樣和逐行掃描輸入 |
| 文件頁(yè)數(shù)： | 31/69頁(yè) |
| 文件大?。?/td> | 664K |
| 代理商： | ADV7192 |
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ADV7192
–31–
REV. 0
MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 58 shows the various operations under the control of Mode
Register 2.
MR2 BIT DESCRIPTION—RGB/YUV Control (MR20)
This bit enables the output from the DACs to be set to YUV or
RGB output video standard.
DAC Output Control (MR21)
This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma and Chroma Signals are output
from DACs A, B, and C (respectively). When this bit is set to 0,
RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC out-
put configurations is shown below.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)
This bit is used to set up square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4
×
Oversampling mode.
Standard I
2
C Control (MR25)
This bit controls the video standard used by the ADV7192.
When this bit is set to 1 the video standard is as programmed in
Mode Register 0 (Output Video Standard Selection). When it is
set to 0, the ADV7192 is forced into the standard selected by
the NTSC_PAL pin. When NTSC_PAL is low, the standard is
NTSC, when the NTSC_PAL pin is high, the standard is PAL.
Pixel Data Valid Control (MR26)
After resetting the device this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7192 will be set to Master Mode
timing. When this bit is set to 1 by the user (via the I
2
C), pixel
data passes to the pins and the encoder reverts to the timing mode
defined by Timing Register 0.
Sleep Mode Control (MR27)
When this bit is set (1), Sleep Mode is enabled. With this mode
cally 0.1
μ
A. The I
2
C registers can be written to and read from
when the ADV7192 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7192 will come out of Sleep Mode and resume normal
operation. Also, if a
RESET
is applied during Sleep Mode the
ADV7192 will come out of Sleep Mode and resume normal
operation.
For this to operate Power up in Sleep Mode control has to be
enabled (MR60 is set to a Logic 0), otherwise Sleep Mode is
controlled by the PAL_NTSC and SCRESET/RTC/TR pins.
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
RGB/YUV
CONTROL
MR20
0
1
RGB OUTPUT
YUV OUTPUT
SCART ENABLE
CONTROL
MR22
0
1
DISABLE
ENABLE
SQUARE PIXEL
CONTROL
MR24
0
1
DISABLE
ENABLE
PIXEL DATA
VALID CONTROL
MR26
0
1
DISABLE
ENABLE
DAC OUTPUT
CONTROL
0
1
RGB/YUV/COMP
COMP/LUMA/CHROMA
MR21
PEDESTAL
CONTROL
0
1
PEDESTAL OFF
PEDESTAL ON
MR23
STANDARD I
2
C
CONTROL
MR25
0
1
DISABLE
ENABLE
SLEEP MODE
CONTROL
MR27
0
1
DISABLE
ENABLE
Figure 58. Mode Register 2, MR2
Table III. DAC Output Configuration
MR22
MR21
MR20
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
G (Y)
Y (Y)
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
B (Pb)
U (Pb)
LUMA
LUMA
B (Pb)
U (Pb)
LUMA
LUMA
R (Pr)
V (Pr)
CHROMA
CHROMA
R (Pr)
V (Pr)
CHROMA
CHROMA
CVBS
CVBS
G (Y)
Y (Y)
G (Y)
Y (Y)
G (Y)
Y (Y)
LUMA
LUMA
B (Pb)
U (Pb)
LUMA
LUMA
B (Pb)
U (Pb)
CHROMA
CHROMA
R (Pr)
V (Pr)
CHROMA
CHROMA
R (Pr)
V (Pr)
NOTE
In Progressive Scan Mode (MR80 = 1) the DAC output configuration is stated in the brackets.
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| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
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