參數(shù)資料
型號(hào)： ADV7192
廠商： Analog Devices, Inc.
英文描述： Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
中文描述： 視頻編碼器與六10位DAC，54兆赫采樣和逐行掃描輸入
文件頁數(shù)： 12/69頁
文件大小： 664K
代理商： ADV7192
ADV7192
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12
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REV. 0
Digital Noise Reduction allows improved picture quality in remov-
ing low amplitude, high frequency noise. Figure 6 shows the DNR
functionality in the two modes available.
Programmable gamma correction is also available. The figure below
shows the response of different gamma values to a ramp signal.
250
200
150
100
50
0
300
SIGNAL OUTPUTS
SGNALINPUT
0.5
GAMMA CORRECTION BLOCK OUTPUT
G
0
50
100
150
200
250
LOCATION
0.3
1.5
1.8
Figure 7. Signal Input (Ramp) and Selectable Gamma
Output Curves
The device is driven by a 27 MHz clock. Data can be output at
27 MHz or 54 MHz (on-board PLL) when 4 oversampling is
enabled. Also, the output filter requirements in 4 oversampling
and 2 oversampling differ, as can be seen in Figure 8.
–
30dB
0dB
6.75MHz
13.5MHz
27.0MHz
40.5MHz
54.0MHz
2 FILTER
REQUIREMENTS
4 FILTER
REQUIREMENTS
Figure 8. Output Filter Requirements in 4
×
Oversampling
Mode
ENCODER
CORE
2
I
N
T
E
R
P
O
L
A
T
I
O
N
6
D
A
C
O
U
T
P
U
T
S
54MHz
OUTPUT
RATE
ADV7192
PLL
54MHz
MPEG2
PIXEL BUS
27MHz
Figure 9. PLL and 4
×
Oversampling Block Diagram
The ADV7192 also supports both PAL and NTSC square pixel
operation. In this case the encoder requires a 24.5454MHz Clock
for NTSC or 29.5 MHz Clock for PAL square pixel mode opera-
tion. All internal timing is generated on-chip.
An advanced power management circuit enables optimal control
of power consumption in normal operating modes or sleep modes.
The Output Video Frames are synchronized with the incoming
data Timing Reference Codes. Optionally, the Encoder accepts
(and can generate)
HSYNC
,
VSYNC,
and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in master mode.
HSO
/
CSO
and
VSO
TTL outputs are also available and are timed
to the analog output video.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7192 also incorporates WSS and CGMS-A data control
generation.
The ADV7192 modes are set up over a 2-wire serial bidirectional
port (I
2
C-compatible) with two slave addresses, and the device
is register-compatible with the ADV7172.
The ADV7192 is packaged in an 80-lead LQFP package.
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N, and NTSCM, N modes, YCrCb
4:2:2 data is input via the CCIR-656/601-compatible Pixel Port
at a 27 MHz Data Rate. The Pixel Data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and Cb
typically have a range of 128 112; however, it is possible to
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7192
supports PAL (B, D, G, H, I, N, M) and NTSCM, N (with
and without Pedestal) and PAL60 standards.
Digital noise reduction can be applied to the Y signal. Pro-
grammable gamma correction can also be applied to the Y
signal if required.
The Y data can be manipulated for contrast control and a setup
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next field when double buffering is
enabled.
The appropriate sync, blank, and burst levels are added to the
YCrCb data. Macrovision antitaping, closed-captioning and
teletext levels are also added to Y and the resultant data is inter-
polated to 54 MHz (4 Oversampling Mode). The interpolated
data is filtered and scaled by three digital FIR filters.
The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto
the color subcarrier during active video to allow hue adjustment.
The resulting U and V signals are added together to make up
the Chrominance signal. The Luma (Y) signal can be delayed
by up to six clock cycles (at 27 MHz) and the Chroma signal
can be delayed by up to eight clock cycles (at 27 MHz).
The Luma and Chroma signals are added together to make up
the Composite Video Signal. All timing signals are controlled.
The YCrCb data is also used to generate RGB data with appropri-
ate sync and blank levels. The YUV levels are scaled to output
the suitable SMPTE/EBU N10, MII, or Betacam levels.
Each DAC can be individually powered off if not required. A
complete description of DAC output configurations is given in
the Mode Register 2 section.
Video output levels are illustrated in Appendix 9.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7192KST 制造商:AD 制造商全稱:Analog Devices 功能描述:Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
ADV7194 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
ADV7194KST 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7194KSTZ 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7194KSTZ 制造商:Analog Devices 功能描述:TV / Video IC
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