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參數(shù)資料
型號： ADV7188BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 106/112頁
文件大?。?/td> 0K
描述： IC DECODER VID MULTIFORM 80LQFP
標準包裝： 1
類型： 視頻解碼器
應用： 機頂盒，視頻播放器，錄音機
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設備封裝： 80-LQFP（14x14）
包裝： 托盤
ADV7188
Rev. A | Page 93 of 112
Bit1
Address
Register
Bit Description
7 6 5 4 3 2 1 0 Comments
Notes
0x69
Configuration 1
0 0 INSEL selects analog input muxing
0 1 Composite—AIN11
1 0 S-video—Y on AIN10 and C on
AIN12
SDM_SEL [1:0]. Y/C and CVBS autodetect
mode select.
1 1 Composite/S-video autodetect
Composite on AIN11
Y on AIN11
C on AIN12
Reserved.
0 0 0 0 0 x
Reserved.
0 1 1 Reserved
0
Disables STDI functionality
STDI_LINE_COUNT_MODE.
1
Enables STDI functionality
0x86
STDI Control
Reserved.
0 0 x 0
Reserved.
0 0 0 0 Set to default
0 0 0
LLC1 (nominally 27 MHz) selected
output on LLC1 pin
LLC_PAD_SEL [2:0]. These bits enable manual
selection of a clock for the LLC1 pin.
1 0 1
LLC2 (nominally 13.5 MHz)
selected output on LLC1 pin
For 16-bit 4:2:2 out, OF_SEL [3:0] = 0010.
0x8F
Free-Run Line
Length 1
Reserved.
0
Set to default
0x99
CCAP1 (Read Only)
CCAP1 [7:0]. Closed caption data bits.
x x x x
x
CCAP1 [7] contains parity bit for
Byte 0
Only for use with VBI System 2
0x9A
CCAP2 (Read Only)
CCAP2 [7:0]. Closed caption data bits.
x x x x
x
CCAP2 [7] contains parity bit for
Byte 0
Only for use with VBI System 2
0x9B
Letterbox 1
(Read Only)
LB_LCT [7:0]. Letterbox data register.
x x x x
x
Reports the number of black lines
detected at the top of active video
0x9C
Letterbox 2
(Read Only)
LB_LCM [7:0]. Letterbox data register.
x x x x
x
Reports the number of black
lines detected in the bottom
half of active video if subtitles
are detected
0x9D
Letterbox 3
(Read Only)
LB_LCB [7:0]. Letterbox data register.
x x x x
x
Reports the number of black
lines detected at the bottom
of active video
This feature examines the active video
at the start and end of each field.,
enabling format detection even if
the video is not accompanied by a
CGMS or WSS sequence.
BL [13:8]. Block length data register.
x x
x
BL [13:0] reports the number of
clock cycles in a block of eight
lines of incoming video
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
Reserved
x
Reserved
0
Indicates that BL [13:0], LCF [10:0],
and LCVS [4:0] are not valid
parameters
0xB1
Standard Ident 1
(Read Only)
STDI_DVALID. Standard identification data
valid readback.
1
Indicates that BL [13:0], LCF [10:0],
and LCVS [4:0] are valid parameters
0xB2
Standard Ident 2
(Read Only)
BL [7:0]. Block length data register.
x x x x
x
BL [13:0] reports the number of
clock cycles in a block of eight
lines of incoming video
LCF [10:8]. Line count in field.
x
Reports the number of lines
between two vsyncs or one field
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
0xB3
Standard Ident 3
(Read Only)
LCVS [4:0].
x x x x
x
Reports the number of lines within
a vertical synchronization period
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
0xB4
Standard Ident 4
(Read Only)
LCF [7:0].
x x x x
x
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
0xC3
ADC Switch 1
0 0 0 0 No connection
0 0 0 1 AIN1
0 0 1 0 AIN2
0 0 1 1 AIN3
0 1 0 0 AIN4
0 1 0 1 AIN5
0 1 1 0 AIN6
0 1 1 1 No connection
1 0 0 0 No connection
1 0 0 1 AIN7
1 0 1 0 AIN8
1 0 1 1 AIN9
1 1 0 0 AIN10
1 1 0 1 AIN11
1 1 1 0 AIN12
ADC0_SW [3:0]. Manual muxing control
for ADC0.
1 1 1 1 No connection
Set ADC_SW_MAN_EN to 1
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