參數(shù)資料
型號： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 72/92頁
文件大?。?/td> 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the look-up table, and bypass/use the flip-flop. See
Table 65 and Table 67.
Table 65. PLAELMx MMR Bit Descriptions
Bit
Value
Description
31:11
Reserved.
10:9
Mux (0) Control (see Table 67).
8:7
Mux (1) Control (see Table 67).
6
Mux (2) Control.
Set
by user to select the
output of mux (0).
Cleared
by user to select
the bit value from PLADIN.
5
Mux (3) Control.
Set
by user to select the
input pin of the particular element.
Cleared
4:1
Look-Up Table Control.
0000
0.
0001
NOR.
0010
B AND NOT A.
0011
NOT A.
0100
A AND NOT B.
0101
NOT B.
0110
EXOR.
0111
NAND.
1000
AND.
1001
EXNOR.
1010
B.
1011
NOT A OR B.
1100
A.
1101
A OR NOT B.
1110
OR.
1111
1.
0
Mux (4) Control.
Set
by user to bypass the flip-
flop.
Cleared
by user to select the flip-flop
(cleared by default).
Rev. A | Page 72 of 92
Table 67. Feedback Configuration
Bit
Value
10:9
00
01
10
11
8:7
00
01
10
11
PLACLK Register
Name
PLACLK
Address
0xFFFF0B40
Default Value
0x00
Access
R/W
PLACLK is a clock selection for the flip-flops of Block 0 and
clock selection for the flip-flops of Block 1.
Table 66. PLACLK MMR Bit Descriptions
Bit
Value
Description
7
Reserved
6:4
Block 1 Clock Source Selection
000
GPIO Clock on P0.5
001
GPIO Clock on P0.0
010
GPIO Clock on P0.7
011
HCLK
100
OCLK (32.768 kHz)
101
Timer1 Overflow
Other
Reserved
3
Reserved
2:0
Block 0 Clock Source Selection
000
GPIO Clock on P0.5
001
GPIO Clock on P0.0
010
GPIO Clock on P0.7
011
HCLK
100
OCLK (32.768 kHz)
101
Timer1 Overflow
Other
Reserved
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
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