參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 57/92頁(yè)
文件大?。?/td> 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
In general, the on-times of the PWM signals in double update
mode can be defined as follows:
On the high side
T
0HH
= (
PWMDAT0
1
/2
+
PWMDAT0
2
/2
+
PWMCH0
1
+
PWMCH0
2
PWMDAT1
1
PWMDAT1
2
) ×
t
CORE
T
0HL
= (
PWMDAT0
1
/2
+
PWMDAT0
2
/2
PWMCH0
1
PWMCH0
2
+
PWMDAT1
1
+
PWMDAT1
2
) ×
t
CORE
where the subscript
1
refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (
d
) are
d
0H
=
T
0HH
/
T
S
= (
PWMDAT0
1
/2
+
PWMDAT0
2
/2
+
PWMCH0
1
+
PWMCH0
2
PWMDAT1
1
PWMDAT1
2
)/
(
PWMDAT0
1
+
PWMDAT0
2
)
On the low side
T
0LH
= (
PWMDAT0
1
/2
+
PWMDAT0
2
/2
+
PWMCH0
1
+
PWMCH0
2
+
PWMDAT1
1
+
PWMDAT1
2
)
×
t
CORE
T
0LL
= (
PWMDAT0
1
/2
+
PWMDAT0
2
/2
PWMCH0
1
PWMCH0
2
PWMDAT1
1
PWMDAT1
2
) ×
t
CORE
where the subscript
1
refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (
d
) are
d
0L
=
T
0LH
/
T
S
= (PWMDAT0
1
/2 +
PWMDAT0
2
/2 +
PWMCH0
1
+
PWMCH0
2
+
PWMDAT1
1
+
PWMDAT1
2
)/(
PWMDAT0
1
+
PWMDAT0
2
)
Rev. A | Page 57 of 92
For the completely general case in double update mode
(see Figure 58), the switching period is given by
T
S
=
(
PWMDAT0
1
+ PWMDAT0
2
) ×
t
CORE
Again, the values of
T
0H
and
T
0L
are constrained to lie between
zero and
T
S
.
PWM signals similar to those illustrated in Figure 57 and
Figure
58 can be produced on the 1H, 1L, 2H, and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a manner
identical to that described for PWMCH0. The PWM controller
does not produce any PWM outputs until all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers have been written
to at least once. Once these registers have been written, internal
counting of the timers in the three-phase timing unit is enabled.
Writing to the PWMDAT0 register starts the internal timing of the
main PWM timer. Provided that the PWMDAT0 register is written
to prior to the PWMCH0, PWMCH1, and PWMCH2 registers in
the initialization, the first PWMSYNC pulse and interrupt (if
enabled) appear 1.5 ×
t
CORE
×
PWMDAT0
seconds after the initial
write to the PWMDAT0 register in single update mode. In double
update mode, the first PWMSYNC pulse appears after
PWMDAT0
×
t
CORE
seconds.
Output Control Unit
The operation of the output control unit is controlled by the
9-bit read/write PWMEN register. This register controls two
distinct features of the output control unit that are directly
useful in the control of electronic counter measures (ECM) or
binary decimal counter measures (BDCM). The PWMEN
register contains three crossover bits, one for each pair of PWM
outputs. Setting Bit 8 of the PWMEN register enables the
crossover mode for the 0H/0L pair of PWM signals, setting
Bit 7 enables crossover on the 1H/1L pair of PWM signals, and
setting Bit 6 enables crossover on the 2H/2L pair of PWM
signals. If crossover mode is enabled for any pair of PWM
signals, the high-side PWM signal from the timing unit (0H, for
example) is diverted to the associated low-side output of the
output control unit so that the signal ultimately appears at the
PWM0
L
pin. Of course, the corresponding low-side output of
the timing unit is also diverted to the complementary high-side
output of the output control unit so that the signal appears at
the PWM0
H
pin. Following a reset, the three crossover bits are
cleared and the crossover mode is disabled on all three pairs of
PWM signals. The PWMEN register also contains 6 bits (Bit 0
to Bit 5) that can be used to individually enable or disable each
of the six PWM outputs. If the associated bit of the PWMEN
register is set, the corresponding PWM output is disabled
regardless of corresponding value of the duty cycle register. This
PWM output signal remains in the off state as long as the
corresponding enable/disable bit of the PWMEN register is set.
The implementation of this output enable function is
implemented after the crossover function.
Following a reset, all six enable bits of the PWMEN register are
cleared, and all PWM outputs are enabled by default. In a
manner identical to the duty cycle registers, the PWMEN is
latched on the rising edge of the PWMSYNC signal. As a result,
changes to this register only become effective at the start of each
PWM cycle in single update mode. In double update mode, the
PWMEN register can also be updated at the midpoint of the
PWM cycle.
In the control of an ECM, only two inverter legs are switched at
any time, and often the high-side device in one leg must be
switched on at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycle values for
two PWM channels (for example, PWMCH0 = PWMCH1) and
setting Bit 7 of the PWMEN register to cross over the 1H/1L
pair of PWM signals, it is possible to turn on the high-side
switch of Phase A and the low-side switch of Phase B at the
same time. In the control of ECM, it is usual for the third
inverter leg (Phase C in this example) to be disabled for a
number of PWM cycles. This function is implemented by
disabling both the 2H and 2L PWM outputs by setting Bit 0
and Bit 1 of the PWMEN register.
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