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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 50/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
COMPARATOR
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrate voltage comparators. The positive input is multiplexed
with ADC2 and the negative input has two options: ADC3 or
DAC0. The output of the comparator can be configured to
generate a system interrupt, can be routed directly to the
programmable logic array, can start an ADC conversion, or can
be on an external pin, CMP
OUT
, as shown in Figure 53.
Rev. A | Page 50 of 92
0
MUX
IRQ
MUX
DAC0
ADC2/CMP0
ADC3/CMP1
P0.0/CMP
OUT
Figure 53. Comparator
Hysteresis
Figure 54 shows how the input offset voltage and hysteresis
terms are defined. Input offset voltage (V
OS
) is the difference
between the center of the hysteresis range and the ground level.
This can either be positive or negative. The hysteresis voltage
(V
H
) is the width of the hysteresis range.
0
COMP
OUT
COMP0
V
H
V
H
V
OS
Figure 54. Comparator Hysteresis Transfer Function
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 29.
CMPCON Register
Name
CMPCON
Address
0xFFFF0444
Default Value
0x0000
Access
R/W
Table 29. CMPCON MMR Bit Descriptions
Bit
Value
Name
15:11
10
CMPEN
Description
Reserved.
Comparator Enable Bit.
Set
by user
to enable the comparator.
Cleared
by user to disable the comparator.
Comparator Negative Input Select
Bits.
AVDD/2.
ADC3 input.
DAC0 output.
Reserved.
Comparator Output Configuration
Bits.
Reserved.
Reserved.
Output on CMP
OUT
.
IRQ.
Comparator Output Logic State Bit.
When low, the comparator output is
high if the positive input (CMP0) is
above the negative input (CMP1).
When high, the comparator output
is high if the positive input is below
the negative input.
Response Time.
5
μ
s response time typical for large
signals (2.5 V differential).
17
μ
s response time typical for small
signals (0.65 mV differential).
3
μ
s typical.
9:8
CMPIN
7:6
00
01
10
11
CMPOC
5
00
01
10
11
CMPOL
4:3
00
CMPRES
11
2
CMPHYST
Comparator Hysteresis Bit.
Se
t by
user to have a hysteresis of about
7.5 mV.
Cleared
by user to have no
hysteresis.
Comparator Output Rising Edge
Interrupt.
Set
automatically when a
rising edge occurs on the moni-
tored voltage (CMP0).
Cleared
by
user by writing a 1 to this bit.
Comparator Output Falling Edge
Interrupt.
Set
automatically when a
falling edge occurs on the monitored
voltage (CMP0).
Cleared
by user.
1
CMPORI
0
CMPOFI
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