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| 型號(hào)： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁(yè)數(shù)： | 70/92頁(yè) |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Table 62. I2C0CFG MMR Bit Descriptions
Bit
Description
31:5
Reserved. These bits should be written by the user as 0.
14
Enable Stop Interrupt.
Set
by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start
condition + matching address.
Cleared
by the user to disable the generation of an interrupt upon receiving a stop condition.
13
Reserved.
12
Reserved.
11
Enable Stretch SCL (Holds SCL Low).
Set
by the user to stretch the SCL line.
Cleared
by the user to disable stretching of the SCL line.
10
Reserved.
9
Slave Tx FIFO Request Interrupt Enable.
Set
by the user to disable the slave Tx FIFO request interrupt.
Cleared
by the user to
generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the
slave Tx FIFO if it is empty. At 400 ksps and the core clock running at 41.78 MHz, the user has 45 clock cycles to take appropriate
action, taking interrupt latency into account.
8
General Call Status Bit Clear.
Set
by the user to clear the general call status bits.
Cleared
automatically by hardware after the general
call status bits have been cleared.
7
Master Serial Clock Enable Bit.
Set
by user to enable generation of the serial clock in master mode.
Cleared
by user to disable serial
clock in master mode.
6
Loop Back Enable Bit.
Set
by user to internally connect the transition to the reception to test user software.
Cleared
by user to
operate in normal mode.
5
Start Back-Off Disable Bit.
Set
by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit.
Cleared
by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit.
4
Hardware General Call Enable. When this bit and the general call enable bit are set, and have received a general call (address 0x00)
and a data byte, the device checks the contents of the I2C0ALT against the receive register. If they match, then the device has
received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which
master it needs to turn to. This is a "to whom it may concern" call. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 watch for
these addresses. The device that requires attention embeds its own address into the message. All masters listen and the master
that knows how to handle the device contacts its slave and acts appropriately. The LSB of the I2C0ALT register should always be
written to a 1, as per I
2
C January 2000 specification.
3
General Call Enable Bit.
Set
this bit to enable the slave device to ACK an I
2
C general call, address 0x00 (write). The device then
recognizes a data bit. If it receives a 0x06 as the data byte, “Reset and write programmable part of slave address by hardware,” then
the I
2
C interface resets as per the I
2
C January 2000 specification. This command can be used to reset an entire I
2
C system. The
general call interrupt status bit sets on any general call. It is up to the user to take correct action by setting up the I
2
C interface after
a reset. If it receives a 0x04 as the data byte, “Write programmable part of slave address by hardware,” then the general call interrupt
status bit sets on any general call. It is up to the user to take correct action by reprogramming the device address.
2
Reserved.
1
Master Enable Bit.
Set
by user to enable the master I
2
C channel.
Cleared
by user to disable the master I
2
C channel.
0
Slave Enable Bit.
Set
by user to enable the slave I
2
C channel. A slave transfer sequence is monitored for the device address in
I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence.
Cleared
by user to disable the slave I
2
C channel.
Rev. A | Page 70 of 92
I2CxDIV Registers
Name
I2C0DIV
I2C1DIV
Address
0xFFFF0830
0xFFFF0930
Default Value
0x1F1F
0x1F1F
Access
R/W
R/W
I2CxDIV are the clock divider registers.
I2CxIDx Registers
Name
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C1ID0
I2C1ID1
I2C1ID2
I2C1ID3
Address
0xFFFF0838
0xFFFF083C
0xFFFF0840
0xFFFF0844
0xFFFF0938
0xFFFF093C
0xFFFF0940
0xFFFF0944
Default Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
I2CxCCNT Registers
Name
I2C0CCNT
I2C1CCNT
Address
0xFFFF0848
0xFFFF0948
Default Value
0x01
0x01
Access
R/W
R/W
I2CxCCNT are 8-bit start/stop generation counters. They hold
off SDA low for start and stop conditions.
I2CxFSTA Registers
Name
I2C0FSTA
I2C1FSTA
Address
0xFFFF084C
0xFFFF094C
Default Value
0x0000
0x0000
Access
R
R
I2CxFSTA are FIFO status registers.
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