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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 45/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
FEECON is an 8-bit
command register. The commands are
described in
Table 21
.
Table 21. Command Codes in FEECON
Code
Command
Description
0x00
1
Null
Idle State.
0x01
1
Single Read
Load FEEDAT with the 16-bit data.
Indexed by FEEADR.
0x02
1
Single Write
Write FEEDAT at the address pointed by
FEEADR. This operation takes 20
μ
s.
0x03
1
Erase/Write
Erase the page indexed by FEEADR and
write FEEDAT at the location pointed by
FEEADR. This operation takes 20 ms.
0x04
1
Single Verify
Compare the contents of the location
pointed by FEEADR to the data in
FEEDAT. The result of the comparison is
returned in FEESTA Bit 1.
0x05
1
Single Erase
Erase the page indexed by FEEADR.
0x06
1
Mass Erase
Erase 62 kB of user space. The 2 kB of
kernel are protected. This operation
takes 2.48 seconds. To prevent accidental
execution, a command sequence is
required to execute this instruction. See
the Command Sequence for Executing a
Mass Erase section.
0x07
Burst Read
Default Command. No write is allowed.
This operation takes two cycles.
0x08
Burst
Read/Write
16 bits and takes a maximum of 8 x 20
μ
s.
0x09
Erase Burst
Read/Write
the write; writes pages without running
an erase command. This command takes
20 ms to erase the page + 20
μ
s per data
to write.
0x0A
Reserved
Reserved.
0x0B
Signature
Give a signature of the 64 kB of Flash/EE
in the 24-bit FEESIGN MMR. This
operation takes 32,778 clock cycles.
0x0C
Protect
This command can run only once. The
value of FEEPRO is saved and removed
only with a mass erase (0x06) or the key.
0x0D
Reserved
Reserved.
0x0E
Reserved
Reserved.
0x0F
Ping
No operation; interrupt generated.
Rev. A | Page 45 of 92
Write can handle a maximum of 8 data of
Automatically erases the page indexed by
1
The FEECON register always reads 0x07 immediately after execution of any
of these commands.
FEEDAT Register
Name
FEEDAT
Address
0xFFFFF80C
Default Value
0xXXXX
Access
R/W
FEEDAT is a 16-bit data register.
FEEADR Register
Name
FEEADR
Address
0xFFFFF810
Default Value
0x0000
Access
R/W
FEEADR is another 16-bit address register.
FEESIGN Register
Name
FEESIGN
Address
0xFFFFF818
Default Value
0xFFFFFF
Access
R
FEESIGN is a 24-bit code signature.
FEEPRO Register
Name
FEEPRO
Address
0xFFFFF81C
Default Value
0x00000000
Access
R/W
FEEPRO MMR provides immediate protection. It does not
require any software keys, see Table 22.
FEEHIDE Register
Name
FEEHIDE
Address
0xFFFFF820
Default Value
0xFFFFFFFF
Access
R/W
FEEHIDE provides protection following subsequent reset of the
MMR. It requires a software key. See description in Table 22.
Table 22. FEEPRO and FEEHIDE MMR Bit Designations
Bit
Description
31
Read Protection.
Cleared
by user to protect all code.
Set
by user to allow reading the code.
30:0
Write Protection for Pages 123 to 120, Pages 119 to 116,
and Pages 0 to 3.
Cleared
by user to protect the pages in
writing.
Set
by user to allow writing the pages.
Command Sequence for Executing a Mass Erase
FEEDAT=0x3CFF;
FEEADR = 0xFFC3;
FEEMOD= FEEMOD|0x8; //Erase key enable
FEECON=0x06;
//Mass erase command
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