參數(shù)資料
型號： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 40/92頁
文件大?。?/td> 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
ADCCN Register
Name
ADCCN
Rev. A | Page 40 of 92
Address
0xFFFF0508
Default Value
0x01
Access
R/W
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 16.
Table 16. ADCCN MMR Bit Designation
Bit
Value
Description
7:5
Reserved
4:0
Negative channel selection bits
00000
ADC0
00001
ADC1
00010
ADC2
00011
ADC3
00100
ADC4
00101
ADC5
00110
ADC6
00111
ADC7
01000
ADC8
01001
ADC9
01010
ADC10
01011
ADC11
01100
DAC0/ADC12
01101
DAC1/ADC13
01110
DAC2/ADC14
01111
DAC3/ADC15
10000
Internal reference (self-diagnostic feature)
Others
Reserved
ADCSTA Register
Name
Address
ADCSTA
0xFFFF050C
Default Value
0x00
Access
R
ADCSTA is an
ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADC
BUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADC
BUSY
goes back low. This information can be
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
ADCDAT Register
Name
ADCDAT
Address
0xFFFF0510
Default Value
0x00000000
Access
R
ADCDAT is an ADC data result register. Hold the 12-bit ADC
result as shown in Figure 39.
ADCRST Register
Name
ADCRST
Address
0xFFFF0514
Default Value
0x00
Access
R/W
ADCRST resets the digital interface of the ADC. Writing any
value to this register resets all the ADC registers to their default
value.
ADCGN Register
Name
ADCGN
Address
0xFFFF0530
Default Value
0x0200
Access
R/W
ADCGN is a 10-bit gain calibration register.
ADCOF Register
Name
ADCOF
Address
0xFFFF0534
Default Value
0x0200
Access
R/W
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three different modes: differential,
pseudo differential, and single-ended.
Differential Mode
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 each
contain a successive approximation ADC based on two
capacitive DACs. Figure 42 and Figure 43 show simplified
schematics of the ADC in acquisition and conversion phase,
respectively. The ADC is comprised of control logic, a SAR, and
two capacitive DACs. In Figure 42 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor
arrays acquire the differential signal on the input.
0
CADAC
CADAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
REF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 42. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 43, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the V
IN+
and V
IN–
pins must
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
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