參數(shù)資料
型號(hào)： ADUC7122BBCZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 82/96頁(yè)
文件大?。?/td> 0K
描述： PRECISION ANALOG MCU I.C
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b，D/A 12x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADUC7122BBCZ-RLDKR
ADuC7122
Rev. 0 | Page 83 of 96
IRQCLRE Register
Name:
IRQCLRE
Address:
0xFFFF0038
Default Value:
0x00000000
Access:
Write only
Table 141. IRQCLRE MMR Bit Designations
Bit
Name
Description
31:26
Reserved
These bits are reserved and should not be
written to.
25
IRQ5CLRI
A 1 must be written to this bit in the IRQ5
interrupt service routine to clear an edge.
24
IRQ4CLRI
A 1 must be written to this bit in the IRQ4
interrupt service routine to clear an edge.
23
Reserved
This bit is reserved and should not be
written to.
22
IRQ3CLRI
A 1 must be written to this bit in the IRQ3
interrupt service routine to clear an edge
triggered IRQ3 interrupt.
21
IRQ2CLRI
A 1 must be written to this bit in the IRQ2
interrupt service routine to clear an edge
triggered IRQ2 interrupt.
20
IRQ1CLRI
A 1 must be written to this bit in the IRQ1
interrupt service routine to clear an edge
triggered IRQ1 interrupt.
19
IRQ0CLRI
A 1 must be written to this bit in the IRQO
interrupt service routine to clear an edge
triggered IRQ0 interrupt.
18:0
Reserved
These bits are reserved and should not be
written to.
TIMERS
The ADuC7122 has five general-purpose timers/counters.
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
The five timers in their normal mode of operation can be either
free-running or periodic.
In free-running mode, the counter decrements/increments
from the maximum/minimum value until zero scale/full scale
and starts again at the maximum/minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero scale/full
scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero if counting down, or full scale if counting
up. An IRQ can be cleared by writing any value to the clear
register of the particular timer (TxCLRI).
The event selection feature allows flexible interrupt generation
based on Timer0 and Timer1. T0CON and T1CON can be used
to configure the interrupt sources, as shown in Table 142. When
either Timer0 or Timer1 expires, an interrupt occurs based on
the event selection in T0CON and T1CON MMRs.
Table 142. Event Selection Numbers
Event Selection
(TxCON[16:12])
Interrupt
Number
Name
00000
2
Timer0
00001
3
Timer1
00010
4
Wake-up timer (Timer2)
00011
5
Watchdog timer (Timer3)
00100
6
Timer4
00101
7
Reserved
00110
8
Power supply monitor
00111
9
Undefined
01000
10
Flash Block 0
01001
11
Flash Block 1
01010
12
ADC
01011
13
UART
01100
14
SPI
01101
15
I2C0 master
01110
16
I2C0 slave
01111
17
I2C1 master
10000
18
I2C1 slave
10001
19
External IRQ0
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose 48-bit count up or a 16-bit count
up/down timer with a programmable prescaler. Timer0 is
clocked from the core clock, with a prescaler of 1, 16, 256, or
32,768. This gives a minimum resolution of 22 ns when the core
is operating at 41.78 MHz and with a prescaler of 1. Timer0 can
also be clocked from the undivided core clock, internal 32 kHz
oscillator, or external 32 kHz crystal.
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD that is loaded into the counter. The
current counter value can be read from T0VAL0. Timer0 has a
capture register (T0CAP) that can be triggered by a selected IRQ’s
source initial assertion. When triggered, the current timer value is
copied to T0CAP, and the timer keeps running. This feature can be
used to determine the assertion of an event with more accuracy
than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when TIMER0
overflows or immediately when T0CLRI is written.
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