參數(shù)資料
型號(hào): ADUC7122BBCZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 20/96頁(yè)
文件大?。?/td> 0K
描述: PRECISION ANALOG MCU I.C
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 126KB(63K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b,D/A 12x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADUC7122BBCZ-RLDKR
ADuC7122
Rev. 0 | Page 27 of 96
ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 3.0 V to 3.6 V
supplies and is capable of providing a throughput of up to 1 MSPS
when the clock source is 41.78 MHz. This block provides the
user with a multichannel multiplexer, differential track-and-
hold, on-chip reference, and ADC.
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of the
following three modes:
Fully differential mode for small and balanced signals
Single-ended mode for any single-ended signals
Pseudo differential mode for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
The converter accepts an analog input range of 0 to VREF when
operating in single-ended mode or pseudo differential mode. In
fully differential mode, the input signal must be balanced around
a common-mode voltage, VCM, in the range 0 V to AVDD, and
with maximum amplitude of 2 VREF (see Figure 12).
AVDD
VCM
0
2VREF
0
87
55
-01
2
Figure 12. Examples of Balanced Signals for Fully Differential Mode
A high precision, low drift, and factory-calibrated 2.5 V reference
is provided on chip. An external reference can also be connected
as described in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in
software. An external CONVST pin, an output generated from
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
If the signal has not been deasserted by the time the ADC
conversion is complete, a second conversion begins
automatically.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC
channel input. This facilitates an internal temperature sensor
channel, measuring die temperature to an accuracy of 3C.
For the ADuC7122, a number of modifications have been made
to the ADC input structure that appears in the ADuC702x
family.
The PADC0 and PADC1 inputs connect to a PGA in pseudo
differential mode and allow for selectable gains from 1 to 5 with
32 steps. The remaining ADC channels can be configured as
single, differential, or pseudo differential. A buffer is provided
before the ADC for measuring internal channels.
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