參數(shù)資料
型號(hào): ADUC7122BBCZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 74/96頁(yè)
文件大?。?/td> 0K
描述: PRECISION ANALOG MCU I.C
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 126KB(63K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b,D/A 12x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADUC7122BBCZ-RLDKR
ADuC7122
Rev. 0 | Page 76 of 96
INTERRUPT SYSTEM
There are 27 interrupt sources on the ADuC7122 that are con-
trolled by the interrupt controller. All interrupts are generated
from the on-chip peripherals, except for the software interrupt
(SWI), which is programmable by the user. The ARM7TDMI
CPU core only recognizes interrupts as one of two types: a
normal interrupt request (IRQ) and a fast interrupt request
(FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through a number of interrupt-related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source, as described in Table 128.
The ADuC7122 contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full vectored interrupt controller is
enabled.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Table 128. IRQ/FIQ1 MMRs Bit Designations
Bit
Description
Comments
0
All interrupts OR’ed (FIQ only)
This bit is set if any FIQ is active
1
Software interrupt
User programmable interrupt source
2
Timer0
General-Purpose Timer0
3
Timer1
General-Purpose Timer1
4
Timer2 or wake-up timer
General-Purpose Timer2 or wake-up timer
5
Timer3 or watchdog timer
General-Purpose Timer3 or watchdog timer
6
Timer4
General-Purpose Timer4
7
Reserved
8
PSM
Power supply monitor
9
Undefined
This bit is not used
10
Flash Control 0
Flash controller for Block 0 interrupt
11
Flash Control 1
Flash controller for Block 1 interrupt
12
ADC
ADC interrupt source bit
13
UART
UART interrupt source bit
14
SPI
SPI interrupt source bit
15
I2C0 master IRQ
I2C master interrupt source bit
16
I2C0 slave IRQ
I2C slave interrupt source bit
17
I2C1 master IRQ
I2C master interrupt source bit
18
I2C1 slave IRQ
I2C slave interrupt source bit
19
XIRQ0 (GPIO IRQ0 )
External Interrupt 0
20
XIRQ1 (GPIO IRQ1)
External Interrupt 1
21
XIRQ2 (GPIO IRQ2 )
External Interrupt 2
22
XIRQ3 (GPIO IRQ3)
External Interrupt 3
23
PWM
PWM trip interrupt source bit
24
XIRQ4 (GPIO IRQ4 )
External Interrupt 4
25
XIRQ5 (GPIO IRQ5)
External Interrupt 5
26
PLA IRQ0
PLA Block 0 IRQ bit
27
PLA IRQ1
PLA Block 1 IRQ bit
1 Applies to IRQEN, FIQEN, IRQCLR, FIQCLR, IRQSTA, and FIQSTA registers.
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