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| 型號： | ADUC7122BBCZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | PRECISION ANALOG MCU I.C |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x12b，D/A 12x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -10°C ~ 95°C |
| 封裝/外殼： | 108-LFBGA，CSPBGA |
| 包裝： | 標準包裝 |
| 其它名稱： | ADUC7122BBCZ-RLDKR |
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ADuC7122
Rev. 0 | Page 45 of 96
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 29.
08
75
5-
03
0
R
DAC0
VREF
AVDD
Figure 29. DAC Structure
As illustrated in Figure 29, the reference source for each DAC is
user-selectable in software. It can be either AVDD or VREF. In 0 V-
to-AVDD mode, the DAC output transfer function spans from 0 V
to the voltage at the AVDD pin. In 0 V-to-VREF mode, the DAC
output transfer function spans from 0 V to the internal 2.5 V
reference, VREF.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the DAC linearity specification
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except Code 0 to Code 100,
and, in 0 V-to-AVDD mode only, Code 3995 to Code 4095.
Linearity degradation near ground and AVDD is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 30.
The dotted line in Figure 30 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 30 represents a transfer function
in 0-to-AVDD mode only. In 0 V-to-VREF mode (with VREF <
AVDD), the lower nonlinearity is similar. However, the upper
portion of the transfer function follows the ideal line right to the
end (VREF in this case, not AVDD), showing no signs of endpoint
linearity errors.
08
75
5-
0
31
AVDD
AVDD – 100mV
100mV
0x00000000
0x0FFF0000
Figure 30. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in
Figure 30 become worse as a function of output loading. The
ADuC7122 data sheet specifications assume a 5 kΩ resistive
load to ground at the DAC output. As the output is forced to
source or sink more current, the nonlinear regions at the top or
bottom (respectively) of Figure 30 become larger. With larger
current demands, this can significantly limit output voltage swing.
The DAC can be configured to retain its output voltage after a
watchdog or software reset by writing to the RSTCFG register.
LDO (LOW DROPOUT REGULATOR)
The ADuC7122 contains an integrated LDO that generates the
core supply voltage (LVDD) of approximately 2.6 V from the
IOVDD supply. Because the LDO is driven from IOVDD, the
IOVDD supply voltage needs to be greater than 2.7 V.
An external compensation capacitor (CT) of 0.47 μF with low
equivalent series resistance (ESR) must be placed very close to
the LVDD pin. This capacitor also acts as a storage of charge
and supplies an instantaneous charge required by the core,
particularly at the positive edge of the core clock (HCLK).
The LVDD voltage generated by the LDO is solely for providing
a supply for the ADuC7122. Therefore, users should not use the
LVDD pin as the power supply pin for any other chip. Also, the
IOVDD pin should have excellent power supply decoupling to
help improve line regulation performance of the LDO.
The LVDD pin has no reverse battery, current limit, or thermal
shutdown protection; therefore, it is essential that users of the
ADuC7122 do not short this pin to ground at anytime during
normal operation or during board manufacture.
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