參數(shù)資料
型號(hào)： ADUC7122BBCZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 69/96頁(yè)
文件大?。?/td> 0K
描述： PRECISION ANALOG MCU I.C
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b，D/A 12x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： ADUC7122BBCZ-RLDKR
ADuC7122
Rev. 0 | Page 71 of 96
SPIRX Register
Name:
SPIRX
Address:
0xFFFF0A04
Default Value:
0x00
Access:
Read
Function:
This 8-bit MMR is the SPI receive register.
SPITX Register
Name:
SPITX
Address:
0xFFFF0A08
Default Value:
0x00
Access:
Write
Function:
This 8-bit MMR is the SPI transmit register.
SPIDIV Register
Name:
SPIDIV
Address:
0xFFFF0A0C
Default Value:
0x1B
Access:
Read/write
Function:
This 8-bit MMR is the SPI baud rate selection
register.
SPI Control Register
Name:
SPICON
Address:
0xFFFF0A10
Default Value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the SPI
peripheral in both master and slave modes.
Table 112. SPICON MMR Bit Designations
Bit
Name
Description
15:14
SPIMDE
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
00 = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been
received by the FIFO.
01 = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have been
received by the FIFO.
10 = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes have
been received by the FIFO.
11 = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full, or four
bytes present.
13
SPITFLH
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit
is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit. When the flush
enable bit is set, the FIFO is cleared within a single microprocessor cycle.
Any writes to the Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
12
SPIRFLH
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. When the
flush enable bit is set, the FIFO is cleared within a single microprocessor cycle.
If this bit is set, all incoming data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
11
SPICONT
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the Tx register. SPICS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.
10
SPILP
Loop back enable bit.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to place in normal mode.
9
SPIOEN
Slave MISO output enable bit.
Set this bit for SPIMISO to operate as normal.
Clear this bit to disable the output driver on the SPIMISO pin. The SPIMISO pin is open-drain when this bit is clear.
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