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參數(shù)資料
| 型號(hào)： | ADUC7032BSTZ-88 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 90/120頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤(pán) |
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ADuC7032-8L
Rev. A | Page 71 of 120
PROGRAMMING THE TIMERS
Understanding synchronization across timer domains also
requires that the user code carefully program the timers when
stopping or starting them. The recommended code controls the
timer block when stopping and starting the timers and when
using different clock domains. This can be critical, especially if
timers are enabled to generate an IRQ or FIQ exception; Timer2
is used as an example.
Halting Timer2
When halting Timer2, it is recommended that the IRQEN
bit for Timer2 be masked (using IRQCLR). This prevents
unwanted IRQs from generating an interrupt in the MCU
before the T2CON control bits have been latched in the Timer2
internal logic.
IRQCLR = WAKEUP_TIMER_BIT;
//Masking interrupts
T2CON=0x00;
//Halting the timer
Starting Timer2
When starting Timer2, it is recommended to first load Timer2
with the required TxLD value. Next, start the timer by setting
the T2CON bits as required. This enables the timer, but only
when the T2CON bits have been latched internally in the
Timer2 clock domain. Therefore, it is advised that a delay of
more than three clock periods (that is, 100 μs for a 32 kHz timer
clock source) be inserted to allow both the T2LD value and the
T2CON value to be latched through the synchronization logic
and reach the Timer2 domain.
After the delay, it is recommended that any (inadvertent)
Timer2 interrupts are now cleared using T2CLRI = 0x00.
Finally, the Timer2 system interrupt can be unmasked by
setting the appropriate bit in the IRQEN MMR. An example
of this code is as follows, with the assumption that Timer2 is
halted:
Example Code
T2LD = 0x1;
//Reload Timer
T2CON = 0x02CF;
//Enable T2—Low
Power
Osc, 32768 prescaler
Delay(100us);
//Include Delay to
ensure T2CON bits take effect
T2CLRI = 0 ;
//*ClearTimerIrq
IRQEN = WAKEUP_TIMER_BIT;
//Unmask Timer2
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose 48-bit count-up, or a 16-bit count-
up/count-down timer with a programmable prescalar. Timer0
can be clocked from either the core clock, the low power
32.768 kHz oscillator, the precision 32.768 kHz oscillator, or an
external 32.768 kHz crystal with a prescalar of 1, 16, 256, or
32,768. This gives a minimum resolution of 48.83 ns when the
core is operating at 20.48 MHz, and with a prescalar of 1.
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD that is loaded into the counter.
The current counter value can be read from T0VAL0. Timer0
has a capture register (T0CAP) that can be triggered by a selected
IRQ source initial assertion. Once triggered, the current timer
value is copied to T0CAP, and the timer keeps running. This
feature can be used to determine the assertion of an event with
more accuracy than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when Timer0
overflows, or immediately when T0CLRI is written.
The Timer0 interface consists of the following six MMRs:
T0LD: 16-bit register that holds the 16-bit value that is
loaded into the counter. Available only in 16-bit mode
T0CAP: 16-bit register that holds the 16-bit value captured by
an enabled IRQ event. Available only in 16-bit mode.
T0VAL0 and T0VAL1: 16-bit and 32-bit registers that hold
the 16 least significant bits (LSBs) and 32 most significant bits
(MSBs), respectively. T0VAL0 and T0VAL1 are read only.
In 16-bit mode, 16-bit T0VAL0 is used. In 48-bit mode, both
the 16-bit T0VAL0 and 32-bit T0VAL1 are used.
T0CLRI: 8-bit register. Writing any value to this register
clears the interrupt. Available only in 16-bit mode.
T0CON: configuration MMR described in Table 54.
TIMER0
VALUE
LOW POWER
32.768kHz OSCILLATOR
PRECISION
32.768kHz OSCILLATOR
EXTERNAL 32.768kHz
WATCH CRYSTAL
CORE
CLOCK FREQUENCY
PRESCALAR
1, 16, 256, OR 32768
TIMER0 IRQ
48-BIT UP COUNTER
16-BIT UP/DOWN COUNTER
16-BIT LOAD
CAPTURE
IRQ[31:0]
059
86
-03
0
Figure 32. Timer0 Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ADUC7032BSTZ-88-RL | 功能描述:IC MCU 96K FLASH DUAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC7032BSTZ-8L | 制造商:Analog Devices 功能描述:FLASH 96K ARM7 TRIPLE 16-BIT ADC LIN IC. - Trays |
| ADUC7032BSTZ-8L-RL | 制造商:Analog Devices 功能描述:FLASH 96K ARM7 TRIPLE 16-BIT ADC LIN IC. - Tape and Reel |
| ADUC7032BSTZ-8V | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| ADUC7032BSTZ-8V-RL | 功能描述:IC BATTERY SENSOR PREC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:8KB（4K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 11x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR) |
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