參數(shù)資料
型號(hào)： ADT7518ARQZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 34/40頁(yè)
文件大小： 891K
描述： IC SENSOR TEMP QD ADC/DAC 16QSOP
標(biāo)準(zhǔn)包裝： 98
功能： 溫度監(jiān)控系統(tǒng)（傳感器）
傳感器類(lèi)型： 內(nèi)部和外部
感應(yīng)溫度： -40°C ~ 120°C，外部傳感器
精確度： ±3°C（最小值）
拓?fù)洌?/td> ADC，比較器，多路復(fù)用器，寄存器庫(kù)
輸出類(lèi)型： I²C?，MICROWIRE?，QSPI?，SPI?
輸出警報(bào)： 無(wú)
輸出風(fēng)扇： 無(wú)
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 120°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 798 (CN2011-ZH PDF)
ADT7518
 
Rev. A | Page 34 of 40
A
B
CS
(START HIGH)
SPI LOCKED ON
THIRD RISING EDGE
C
SPI FRAMING
EDGE
A
B
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
C
SPI FRAMING
EDGE
 
Figure 53. Serial InterfaceSelecting and Locking SPI Protocol
 
To select and lock the interface into the SPI mode, a number of
pulses must be sent down the CS
 line (Pin 4). The following
section describes how this is done.
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI lock status register (Address 7Fh) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and
power it up again. A software reset does not reset the serial
interface.
Serial Interface Selection
The
CS
 line controls the selection between I
2
C and SPI.
Figure 53 shows the selection process necessary to lock the SPI
interface mode.
To communicate to the ADT7518 using the SPI protocol, send
three pulses down the
CS
 line as shown in Figure 53. On the
third rising edge (marked as C in Figure 53), the part selects and
locks the SPI interface. The user is now limited to communi-
cating to the device using the SPI protocol.
As per most SPI standards, the CS line must be low during
every SPI communication to the ADT7518 and high all other
times. Typical examples of how to connect the dual interface as
I
2
C or SPI is shown in Figure 54 and Figure 55. The following
sections describe in detail how to use the I
2
C and SPI protocols
associated with the ADT7518.
ADT7518
CS
SDA
SCL
ADD
V
DD
V
DD
I
2
C ADDRESS = 1001 000
10k&
10k&
 
Figure 54. Typical I
2
C Interface Connection
ADT7518
SCLK
DOUT
CS
V
DD
LOCK AND
SELECT SPI
SPI FRAMING
EDGE
820&
820&
820&
DIN
 
Figure 55. Typical SPI Interface Connection
I
2
C Serial Interface
Like all I
2
C-compatible devices, the ADT7518 has a 7-bit serial
address. The four MSBs of this address for the ADT7518 are set
to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
address 1001 010, and setting it high gives the address 1001 011.
The recommended pull-up resistor value is 10 k&.
There is an enable/disable bit for the SMBus timeout. When this
is enabled, the SMBus will time out after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-on default is with the SMBus timeout disabled.
The ADT7518 supports SMBus packet error checking (PEC),
but its use is optional. It is triggered by supplying the extra
clocks for the PEC byte. The PEC is calculated using CRC-8.
The frame clock sequence (FCS) conforms to CRC-8 by the
polynominal
( )
1
1
2
8
+
+
+
=
x
x
x
x
C
 
Consult the SMBus specification (www.smbus.org) for more
information.
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