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參數(shù)資料
| 型號： | ADT7518ARQZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 891K |
| 描述： | IC SENSOR TEMP QD ADC/DAC 16QSOP |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部和外部 |
| 感應(yīng)溫度： | -40°C ~ 120°C，外部傳感器 |
| 精確度： | ±3°C（最小值） |
| 拓?fù)洌?/td> | ADC，比較器，多路復(fù)用器，寄存器庫 |
| 輸出類型： | I²C?，MICROWIRE?，QSPI?，SPI? |
| 輸出警報(bào)： | 無 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 120°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 798 (CN2011-ZH PDF) |
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ADT7518
Rev. A | Page 30 of 40
DAC Configuration Register (Read/Write)
[Address = 1Bh]
This configuration register is an 8-bit read/write register that is
used to control the output ranges of all four DACs and also to
control the loading of the DAC registers if the LDAC
pin is
disabled (Bit C3 = 1, Control Configuration 3 register).
Table 35. DAC Configuration
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
* Default settings at power-up
Table 36.
Bit
Function
D0
Selects the output range of DAC A.
0 = 0 V to VREF.
1 = 0 V to 2V
REF
.
D1
Selects the output range of DAC B.
0 = 0 V to VREF.
1 = 0 V to 2V
REF
.
D2
Selects the output range of DAC C.
0 = 0 V to V
REF
.
1 = 0 V to 2V
REF
.
D3
Selects the output range of DAC D.
0 = 0 V to V
REF
.
1 = 0 V to 2V
REF
.
D5:D4 00 = A write to any DAC register generates LDAC
command that updates that DAC only.
01 = A write to DAC B or DAC D register generates
LDAC command that updates DACs A, B or DACs C, D,
respectively.
10 = A write to DAC D register generates LDAC
command that updates all four DACs.
11 = LDAC command generated from LDAC register.
D6:D7 Reserved. Write 0s only.
LDAC Configuration Register (Write-Only)
[Address = 1Ch]
This configuration register is an 8-bit write register that is used
to control the updating of the quad DAC outputs if the LDAC
pin is disabled and Bits D4:D5 of the DAC configuration reg-
ister are both set to 1. Also selects either the internal or external
V
REF
for all four DACs. Bits D0:D3 in this register are self-clear-
ing, i.e., reading back from this register will always give 0s for
these bits.
Table 37. LDAC Configuration
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
* Default settings at power-up
Table 38.
Bit
Function
D0
Writing a 1 to this bit will generate the LDAC command
to update DAC A output only.
D1
Writing a 1 to this bit will generate the LDAC command
to update DAC B output only.
D2
Writing a 1 to this bit will generate the LDAC command
to update DAC C output only.
D3
Writing a 1 to this bit will generate the LDAC command
to update DAC D output only.
D4
Selects either internal VREF or external VREF for DACs A
and B.
0 = External VREF
1 = Internal V
REF
.
D5
Selects either internal VREF or external VREF for DACs C
and D.
0 = External V
REF
1 = Internal V
REF
D6:D7 Reserved. Write 0s only.
Interrupt Mask 1 Register (Read/Write) [Address = 1Dh]
This mask register is an 8-bit read/write register that can be
used to mask any interrupts that can cause the INT/INT
pin to
go active.
Table 39. Interrupt Mask 1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
* Default settings at power-up
Table 40.
Bit Function
D0 0 = Enable internal THIGH interrupt.
1 = Disable internal THIGH interrupt.
D1 0 = Enable internal T
LOW
interrupt.
1 = Disable internal TLOW interrupt.
D2 0 = Enable external T
HIGH
interrupt or AIN1 interrupt.
1 = Disable external T
HIGH
interrupt or AIN1 interrupt.
D3 0 = Enable external T
LOW
interrupt.
1 = Disable external T
LOW
interrupt.
D4 0 = Enable external temperature fault interrupt..
1 = Disable external temperature fault interrupt.
D5 0 = Enable AIN2 interrupt.
1 = Disable AIN2 interrupt.
D6 0 = Enable AIN3 interrupt.
1 = Disable AIN3 interrupt.
D7 0 = Enable AIN4 interrupt.
1 = Disable AIN4 interrupt.
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