ADT7518
Rev. A | Page 33 of 40
AIN2 V
LOW
Limit Register (Read/Write) [Address = 2Ch]
This limit register is an 8-bit read/write register that stores the
AIN2 input lower limit, which will cause an interrupt and acti-
vate the INT/INT
output (if enabled). For this to happen, the
measured AIN2 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
Table 54. AIN2 V
LOW
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
* Default settings at power-up
AIN3 V
HIGH
Limit Register (Read/Write) [Address = 2Dh]
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit, which will cause an interrupt and acti-
vate the INT/INT
output (if enabled). For this to happen, the
measured AIN3 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Table 55. AIN3 VHIGH Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
1*
1*
1*
1*
1*
1*
* Default settings at power-up
AIN3 VLOW Limit Register (Read/Write) [Address = 2Eh]
This limit register is an 8-bit read/write register that stores the
AIN3 input lower limit, which will cause an interrupt and
activate the INT/INT
output (if enabled). For this to happen,
the measured AIN3 value has to be less than or equal to the
value in this register. Because it is an 8-bit register, the reso-
lution is four times less than the resolution of the 10-bit ADC.
The default value is 0 V.
Table 56. AIN3 V
LOW
Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
* Default settings at power-up
AIN4 VHIGH Limit Register (Read/Write) [Address = 2Fh]
This limit register is an 8-bit read/write register that stores the
AIN4 input upper limit, which will cause an interrupt and acti-
vate the INT/
INT
output (if enabled). For this to happen, the
measured AIN4 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Table 57. AIN4 VHIGH Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1*
1*
1*
1*
1*
1*
1*
1*
* Default settings at power-up
AIN4 V
LOW
Limit Register (Read/Write) [Address = 30h]
This limit register is an 8-bit read/write register that stores the
AIN4 input lower limit, which will cause an interrupt and
activate the INT/INT
output (if enabled). For this to happen,
the measured AIN4 value has to be less than or equal to the
value in this register. Because it is an 8-bit register, the reso-
lution is four times less than the resolution of the 10-bit ADC.
The default value is 0 V.
Table 58. AIN4 VLOW Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
* Default settings at power-up
Device ID Register (Read-Only) [Address = 4Dh]
This 8-bit read-only register contains a device identifier byte:
ADT7518 = 0Bh.
Manufacturers ID Register (Read-Only) [Address = 4Eh]
This register contains the manufacturers identification number.
ADIs ID number is 41h.
Silicon Revision Register (Read-Only) [Address = 4Fh]
This register is divided into four LSBs representing the stepping
and the four MSBs representing the version. The stepping con-
tains the manufacturers code for minor revisions or steppings
to the silicon. The version is the ADT7518 version number.
SPI Lock Status Register (Read-Only) [Address = 7Fh]
Bit D0 (LSB) of this read-only register indicates whether or not
the SPI interface is locked. Writing to this register will cause the
device to malfunction. The default value is 00h.
0 = I
2
C interface.
1 = SPI interface selected and locked.
SERIAL INTERFACE
There are two serial interfaces that can be used on this part: I
2
C
and SPI. The device will power up with the serial interface in
I
2
C mode, but it is not locked into this mode. To stay in I
2
C
mode, it is recommended that the user tie the CS
line to either
V
CC
or GND. It is not possible to lock the I
2
C mode, but it is
possible to select and lock the SPI mode.