ADT7518
 
Rev. A | Page 21 of 40 
The ADC resolution is 10 bits and is mostly suitable for dc input 
signals. Bits C1:2 of the Control Configuration 1 register 
(Address 18h) are used to set up Pins 7 and 8 as AIN1 and 
AIN2. Figure 44 shows the overall view of the 4-channel analog 
input path. 
ADC TRANSFER FUNCTION 
The output coding of the ADT7518 analog inputs is straight 
binary. The designed code transitions occur midway between 
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB). The LSB is 
VDD/1024 or internal VREF/1024, internal VREF = 2.25 V. The ideal 
transfer characteristic is shown in Figure 47. 
M
U
L
T
I
P
L
E
X
E
R
10-BIT
ADC
TO ADC
VALUE
REGISTER
AIN1
AIN2
AIN3
AIN4
 
111...111
111...110
111...000
011...111
+V
REF
 1LSB
0V 1/2LSB
ANALOG INPUT
1LSB = INT V
REF
/1024
1LSB = V
DD
/1024
000...010
000...001
000...000
 
Figure 44. Quad Analog Input Path 
Converter Operation 
The analog input channels use a successive approximation ADC 
based on a capacitor DAC. Figure 45 and Figure 46 show 
simplified schematics of the ADC. Figure 45 shows the ADC 
during acquisition phase. SW2 is closed and SW1 is in position 
A. The comparator is held in a balanced condition and the 
sampling capacitor acquires the signal on AIN. 
Figure 47. Single-Ended Transfer Function  
To work out the voltage on any analog input channel, the 
following method can be used:  
CONTROL
LOGIC
CAP DAC
ACQUISITION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
IN
SW1
A
B
SW2
REF/2
 
1 LSB = reference (v)/1024  
Convert the value read back from the AIN value register into a 
decimal format.  
( )
size
LSB
d
value
AIN
voltage
AIN
?/DIV>
 
d = decimal 
Example: 
Figure 45. ADC Acquisition Phase 
CONTROL
LOGIC
CAP DAC
CONVERSION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT V
REF
REF
V
DD
IN
SW1
A
B
SW2
REF/2
 
Internal reference used. Therefore V
REF
 = 2.25 V. 
AIN value = 512d 
3
10
197
.
2
1024
/
25
.
2
1
?/DIV>
=
=    V
size
LSB
 
V
voltage
AIN
125
.
1
10
197
.
2
512
3
=
?/DIV>
?/DIV>
=
 
 
Analog Input ESD Protection 
Figure 48 shows the input structure on any of the analog input 
pins that provides ESD protection. The diode provides the main 
ESD protection for the analog inputs. Care must be taken that 
the analog input signal never drops below the GND rail by 
more than 200 mV. If this happens, the diode will become 
forward-biased and start conducting current into the substrate. 
The 4 pF capacitor is the typical pin capacitance and the resistor 
is a lumped component made up of the on-resistance of the 
multiplexer switch. 
Figure 46. ADC Conversion Phase 
When the ADC eventually goes into conversion phase (see 
Figure 46), SW2 opens and SW1 moves to position B, causing 
the comparator to become unbalanced. The control logic and 
the DAC are used to add and subtract fixed amounts of charge 
from the sampling capacitor to bring the comparator back into 
a balanced condition. When the comparator is rebalanced, the 
conversion is complete. The control logic generates the ADC 
output code. Figure 47 shows the ADC transfer function for the 
analog inputs. 
4pF
IN
100&
 
Figure 48. Equivalent Analog Input ESD Circuit 
 
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