參數(shù)資料
型號(hào): ADT7476AARQZ-R
廠商: ON Semiconductor
文件頁數(shù): 23/66頁
文件大?。?/td> 945K
描述: IC REMOTE THERMAL CTLR 24QSOP
產(chǎn)品變化通告: MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標(biāo)準(zhǔn)包裝: 2,500
系列: dBCool®
功能: 風(fēng)扇控制,溫度監(jiān)控器
傳感器類型: 內(nèi)部和外部
感應(yīng)溫度: -40°C ~ 125°C
精確度: ±2.5%
拓?fù)洌?/td> ADC,比較器,風(fēng)扇速度計(jì)數(shù)器,多路復(fù)用器,寄存器庫
輸出類型: SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
其它名稱: ADT7476AARQZ-R-ND
ADT7476AARQZ-ROSTR
ADT7476A
http://onsemi.com
23
THERM
 Timer
The ADT7476A has an internal timer to measure THERM
assertion time. For example, the THERM
  input can be
connected to the PROCHOT
 output of a Pentium
?/DIV>
4 CPU to
measure system performance. The THERM
 input can also
be connected to the output of a trip-point temperature sensor.
The timer is started on the assertion of the ADT7476As
THERM
 input and stopped when THERM
 is de-asserted.
The timer counts THERM
 times cumulatively; that is, the
timer resumes counting on the next THERM
 assertion. The
THERM
 timer continues to accumulate THERM
 assertion
times until the timer is read (where it is cleared), or until it
reaches full scale. If the counter reaches full scale, it stops
at that reading until cleared.
The 8-bit THERM
 timer status register (0x79) is designed
so that Bit 0 is set to 1 on the first THERM
 assertion. Once
the cumulative THERM
  assertion time has exceeded
45.52 ms, Bit 1 of the THERM
 timer is set and Bit 0 now
becomes the LSB of the timer with a resolution of 22.76 ms
(see Figure 32).
Figure 32. Understanding the THERM
 Timer
THERM
 ASSERTED
?2.76 ms
THERM
 ASSERTED
?5.52 ms
THERM
 ASSERTED
?13.8 ms
(91.04 ms + 22.76 ms)
THERM
THERM
THERM
TIMER
(REG. 0x79)
THERM
TIMER
(REG. 0x79)
THERM
THERM
TIMER
(REG. 0x79)
ACCUMULATE THERM
 LOW
ASSERTION TIMES
ACCUMULATE THERM
 LOW
ASSERTION TIMES
1
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
1
0
0
0
0
0
0
0
1
2
3
4
5
6
7
1
0
1
0
0
0
0
0
0
1
2
3
4
5
6
7
When using the THERM
 timer, be aware of the following:
After a THERM
 timer read (0x79)
1. The contents of the timer are cleared on read.
2. The F4P bit (Bit 5) of Interrupt Status Register 2
needs to be cleared (assuming that the THERM
timer limit has been exceeded).
If the THERM
 timer is read during a THERM
 assertion, the
following occurs:
1. The contents of the timer are cleared.
2. Bit 0 of the THERM
 timer is set to 1, because a
THERM
 assertion is occurring.
3. The THERM
 timer increments from zero.
4. If the THERM
 timer limit register (0x7A) = 0x00,
the F4P bit is set.
Generating SMBALERT
 Interrupts from THERM
 Timer
Events
The ADT7476A can generate SMBALERT
s when a
programmable THERM
 timer limit has been exceeded. This
allows the system designer to ignore brief, infrequent
THERM
 assertions, while capturing longer THERM
 timer
events. Register 0x7A is the THERM
 timer limit register.
This 8-bit register allows a limit from 0 sec (first THERM
assertion) to 5.825 sec to be set before an SMBALERT
 is
generated. The THERM
 timer value is compared with the
contents of the THERM
 timer limit register. If the THERM
timer value exceeds the THERM
 timer limit value, then the
F4P bit (Bit 5) of Interrupt Status Register 2 is set and an
SMBALERT
 is generated.
NOTE: Depending on which pins are configured as a THERM
 timer,
setting the F4P bit (Bit 5) of Mask Register 2 (0x75) or Bit 0
of Mask Register 1 (0x74) masks out SMBALERT
; although
the F4P bit of Interrupt Status Register 2 is still set if the
THERM
 timer limit is exceeded.
Figure 33 is a functional block diagram of the THERM
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM
  timer limit register (0x7A) causes an
SMBALERT
 to be generated on the first THERM
 assertion.
A THERM
  timer limit value of 0x01 generates an
SMBALERT
 once cumulative THERM
 assertions exceed
45.52 ms.
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