參數(shù)資料
型號(hào)： ADT7476AARQZ-R
廠商： ON Semiconductor
文件頁數(shù)： 21/66頁
文件大?。?/td> 945K
描述： IC REMOTE THERMAL CTLR 24QSOP
產(chǎn)品變化通告： MFG CHG Notification ADI to ON Semi
QSOP 24ld Pkg (MSL) Change 17/Jun/2010
標(biāo)準(zhǔn)包裝： 2,500
系列： dBCool®
功能： 風(fēng)扇控制，溫度監(jiān)控器
傳感器類型： 內(nèi)部和外部
感應(yīng)溫度： -40°C ~ 125°C
精確度： ±2.5%
拓?fù)洌?/td> ADC，比較器，風(fēng)扇速度計(jì)數(shù)器，多路復(fù)用器，寄存器庫
輸出類型： SMBus?
輸出警報(bào)： 無
輸出風(fēng)扇： 是
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 24-QSOP
包裝： 帶卷 (TR)
其它名稱： ADT7476AARQZ-R-ND
ADT7476AARQZ-ROSTR
ADT7476A
http://onsemi.com
21
Table 29. INTERRUPT STATUS REGISTER 2 (0x42)
Bit
Mnemonic
Description
[7]
D2
1 indicates an open or short on
D2+/D2 inputs.
[6]
D1
1 indicates an open or short on
D1+/D1 inputs.
[5]
F4P
1 indicates Fan 4 has dropped below
minimum speed. Alternatively, indicates
that the THERM
 limit has been
exceeded, if the THERM
 function is
used. Alternatively, indicates the status
of GPIO6.
[4]
FAN3
1 indicates that Fan 3 has dropped
below minimum speed.
[3]
FAN2
1 indicates that Fan 2 has dropped
below minimum speed.
[2]
FAN1
1 indicates that Fan 1 has dropped
below minimum speed.
[1]
OVT
1 indicates that a THERM
overtemperature limit has been
exceeded.
[0]
12 V/VC
1 indicates a 12 V high or low limit has
been exceeded. If the VID code change
function is used, this bit indicates a
change in VID code on the VID0 to
VID4 inputs.
SMBALERT
 Interrupt Behavior
The ADT7476A can be polled for status, or an
SMBALERT
 interrupt can be generated for out-of-limit
conditions. It is important to note how the SMBALERT
output and status bits behave when writing interrupt handler
software.
Figure 29. SMBALERT
 and Status Bit Behavior
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
SMBALERT
Figure 29 shows how the SMBALERT
 output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky because they
remain set until read by software. This ensures that an
out-of-limit event cannot be missed if the software is
periodically polling the device.
Note that:
?SPAN class="pst ADT7476AARQZ-R_2298076_4"> The SMBALERT
 output remains low for the entire
duration that a reading is out-of-limit and until the
status register has been read. This has implications on
how software handles the interrupt.
?SPAN class="pst ADT7476AARQZ-R_2298076_4"> THERM
 overtemperature events are not sticky. They
reset immediately after the overtemperature condition
ceases.
Handling SMBALERT
 Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommend to handle the SMBALERT
interrupt as follows:
1. Detect the SMBALERT
 assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(0x74 and 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT
 output and status bits to behave
as shown in Figure 30.
Figure 30. How Masking the Interrupt Source Affects
SMBALERT
 Output
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT
 RE-ARMED)
Masking Interrupt Sources
Interrupt Mask Register 1 (0x74) and Interrupt Mask
Register 2 (0x75) allow individual interrupt sources to be
masked to prevent SMBALERT
 interrupts.
NOTE: Masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
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