參數(shù)資料
型號: ADSP-BF548MBBCZ-5M
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 533 MHz Blackfin Embedded Processor: ADSP-BF548MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1
中文描述: 16-BIT, 50 MHz, OTHER DSP, PBGA400
封裝: 17 X 17 MM, ROHS COMPLIANT, CSBGA-400
文件頁數(shù): 74/100頁
文件大?。?/td> 3095K
代理商: ADSP-BF548MBBCZ-5M
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
|
Page 75 of 100
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May 2011
Register and PIO
Table 58 and Figure 48 describe the ATAPI register and the PIO
data transfer timing. The material in this figure is adapted from
ATAPI-6 (INCITS 361-2002[R2007] and is used with permis-
sion of the American National Standards Institute (ANSI) on
behalf of the Information Technology Industry Council
(“ITIC”). Copies of ATAPI-6 (INCITS 361-2002 [R2007] can be
purchased from ANSI.
Note that in Figure 48 ATAPI_ADDR pins include A1-3,
ATAPI_CS0, and ATAPI_CS1. Alternate ATAPI port
ATAPI_ADDR pins include ATAPI_A0A, ATAPI_A1A,
ATAPI_A2A, ATAPI_CS0, and ATAPI_CS1. Note that an
alternate ATAPI_D0-15 port bus is ATAPI_D0-15A
Table 58. ATAPI Register and PIO Data Transfer Timing
ATAPI Parameter/Description
ATAPI_REG/PIO_TIM_x Timing Register
Setting1
Timing Equation
t0
Cycle time
T2_PIO, TEOC_PIO
(T2_PIO + TEOC_PIO) × tSCLK
t1
ATAPI_ADDR valid to
ATAPI_DIOR/ATAPI_DIOW setup
T1
T1 × tSCLK – (tSK1 + tSK2 + tSK4)
t2
ATAPI_DIOR/ATAPI_DIOW pulse width
T2_PIO
T2_PIO × tSCLK
t2i
ATAPI_DIOR/ATAPI_DIOW recovery time
TEOC_PIO
TEOC_PIO × tSCLK
t3
ATAPI_DIOW data setup
T2_PIO
T2_PIO × tSCLK – (tSK1 + tSK2 + tSK4)
t4
ATAPI_DIOW data hold
T4
T4 × tSCLK – (tSK1 + tSK2 + tSK4)
t5
ATAPI_DIOR data setup
N/A
tOD + tSUD + 2 × tBD + tCDD + tCDC
t6
ATAPI_DIOR data hold
N/A
0
t9
ATAPI_DIOR/ATAPI_DIOW to ATAPI_ADDR
valid hold
TEOC_PIO
TEOC_PIO × tSCLK – (tSK1 + tSK2 + tSK4)
tA
ATAPI_IORDY setup time
T2_PIO
T2_PIO × tSCLK – (tOD + tSUI + 2 × tCDC + 2 × tBD)
1 ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for the ATA device mode of
operation.
Figure 48. REG and PIO Data Transfer Timing
ATAPI
ADDR
t0
t2
t9
t3
t4
t5
tA
t6
t2i
t1
ATAPI_DIOR/
ATAPI_DIOW
ATAPI_D0–15
ATAPI_IORDY
ATAPI_D0–15
(WRITE)
(READ)
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