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參數(shù)資料
| 型號： | ADSP-BF548MBBCZ-5M |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 533 MHz Blackfin Embedded Processor: ADSP-BF548MBBCZ-5M Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| 中文描述： | 16-BIT, 50 MHz, OTHER DSP, PBGA400 |
| 封裝： | 17 X 17 MM, ROHS COMPLIANT, CSBGA-400 |
| 文件頁數(shù)： | 10/100頁 |
| 文件大?。?/td> | 3095K |
| 代理商： | ADSP-BF548MBBCZ-5M |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. D
|
Page 17 of 100
|
May 2011
CLOCK SIGNALS
The ADSP-BF54x Blackfin processors can be clocked by an
external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF54x Blackfin processors
include an on-chip oscillator circuit, an external crystal may be
used. For fundamental frequency operation, use the circuit
shown in Figure 7. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal is connected across the CLKIN
and XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Typically, further parallel
resistors are not recommended. The two capacitors and the
series resistor shown in Figure 7 fine-tune phase and amplitude
of the sine frequency. The 1MOhm pull-up resistor on the
XTAL pin guarantees that the clock circuit is properly held inac-
tive when the processor is in the hibernate state.
The capacitor and resistor values shown in Figure 7 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. System designs should
verify the customized values based on careful investigations on
multiple devices over temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 7. A design procedure for third-overtone oper-
ation is discussed in detail in an Application Note, Using Third
Overtone Crystals (EE-168).
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 8 on Page 17, the core clock
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable 0.5× to 64×
multiplication factor (bounded by specified minimum and max-
imum VCO frequencies). The default multiplier is 8×, but it can
be modified by a software instruction sequence. This sequence
is managed by the bfrom_SysControl() function in the on-chip
ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
Whereas the maximum allowed CCLK and SCLK rates depend
on the applied voltages VDDINT and VDDEXT, the VCO is always
permitted to run up to the frequency specified by the part’s
speed grade.
The CLKOUT pin reflects the SCLK frequency to the off-chip
world. It functions as a reference for many timing specifications.
While inactive by default, it can be enabled using the
EBIU_AMGCTL register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios. The default
ratio is 4.
Figure 6. Voltage Regulator Circuit
VDDVR
(LOW-INDUCTANCE)
VDDINT
VROUT
100μF
VROUT
GND
SHORT AND LOW-
INDUCTANCE WIRE
VDDVR
+
100μF
10μF
LOW ESR
100nF
SETOFDECOUPLING
CAPACITORS
FDS9431A
ZHCS1000
2.7V TO 3.6V
INPUT VOLTAGE
RANGE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
10μH
Figure 7. External Crystal Connections
Note: For CCLK and SCLK specifications, see Table 15.
Figure 8. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
EN
CLKBUF
TO PLL CIRCUITRY
FR OVERTONE
OPERA
O
TION ONLY
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
18 pF*
EN
18 pF*
700
0
BLACKFIN
0
*
VDDEXT
1M
PLL
0.5x - 64x
1:15
1, 2, 4, 8
VCO
CLKIN
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
DYNAMIC MODIFICATION
ON-THE-FLY
CCLK
SCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-BF548BBCZ-5A | 533 MHz Blackfin Embedded Processor: ADSP-BF548BBCZ-5A Temp Range: –40°C to +85°C Package: 400-Ball CSP_BGA BC-400-1 |
| ADSP-TS101SAB1-000 | 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM; Package: 625 ball BGA; No of Pins: 625; Temperature Range: Ind |
| ADSP-TS101SAB2-000 | 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM; Package: 484 ball BGA; No of Pins: 484; Temperature Range: Ind |
| ADSP-TS203SABP-050 | 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind |
| ADSP-TS203SABPZ050 | 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF549BBCZ | 制造商:Analog Devices 功能描述: |
| ADSP-BF549BBCZ-ENG | 制造商:Analog Devices 功能描述:- Bulk |
| adsp-bf5615bbz600 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ADSP-BF561KBCZ-600 | 制造商:Analog Devices 功能描述: |
| ADSP-BF561SBB500 | 功能描述:IC PROCESSOR 500MHZ 297PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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