參數(shù)資料
型號： ADSP-21479KSWZ-2A
廠商： Analog Devices Inc
文件頁數(shù)： 32/72頁
文件大?。?/td> 0K
描述： IC DSP SHARC 266MHZ LP 100LQFP
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART
時鐘速率： 266MHz
非易失內(nèi)存： ROM（4Mb）
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-LQFP-EP（14x14）
包裝： 托盤
其它名稱： Q6418433
Rev. A
|
Page 38 of 72
|
September 2011
Serial Ports
In slave transmitter mode and master receiver mode, the maxi-
mum serial port frequency is fPCLK/8. In master transmitter
mode and slave receiver mode, the maximum serial port clock
frequency is fPCLK/4.
To determine whether communication is possible between two
devices at clock speed, n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 33. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
2.5
ns
tHFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
2.5
ns
tSDRE
1
Receive Data Setup Before Receive SCLK
2.5
ns
tHDRE
1
Receive Data Hold After SCLK
2.5
ns
tSCLKW
SCLK Width
(tPCLK × 4) ÷ 2 – 1.5
ns
tSCLK
SCLK Period
tPCLK × 4
ns
Switching Characteristics
tDFSE
2
Frame Sync Delay After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode)
15
ns
tHOFSE
2
Frame Sync Hold After SCLK
(Internally Generated Frame Sync in Either Transmit or Receive Mode)
2
ns
tDDTE
2
Transmit Data Delay After Transmit SCLK
15
ns
tHDTE
2
Transmit Data Hold After Transmit SCLK
2
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 34. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
10.5
ns
tHFSI
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in Either Transmit or Receive Mode)
2.5
ns
tSDRI
1
Receive Data Setup Before SCLK
10.5
ns
tHDRI
1
Receive Data Hold After SCLK
2.5
ns
Switching Characteristics
tDFSI
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode)
5
ns
tHOFSI
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode)
–1.0
ns
tDFSIR
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode)
10.7
ns
tHOFSIR
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode)
–1.0
ns
tDDTI
2
Transmit Data Delay After SCLK
4
ns
tHDTI
2
Transmit Data Hold After SCLK
–1.0
ns
tSCKLIW
Transmit or Receive SCLK Width
2 × tPCLK – 1.5
2 × tPCLK + 1.5
ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
相關(guān)PDF資料
PDF描述
TAJC106M035SNJ CAP TANT 10UF 35V 20% 2312
GBM08DSEF-S243 CONN EDGECARD 16POS .156 EYELET
M24308/4-5 CONN D-SUB PLUG 50POS CRIMP
NTV1212MC CONV DC/DC 1W 12VIN 12V DL 3KV
VI-B1Z-CY-F3 CONVERTER MOD DC/DC 2V 20W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21479SBC2-EP 功能描述:IC DSP SHARC 266MHZ LP 制造商:analog devices inc. 系列:SHARC? 包裝:托盤 零件狀態(tài):在售 類型:浮點 接口:DAI，DPI，EBI/EMI，I2C，SPI，SPORT，UART/USART 時鐘速率:266MHz 非易失性存儲器:ROM（4Mb） 片載 RAM:5Mb 電壓 - I/O:3.30V 電壓 - 內(nèi)核:1.20V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標準包裝:1
ADSP-21483KSWZ-2B 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21483KSWZ-3AB 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21483KSWZ-3B 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21483KSWZ-4B 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*