參數(shù)資料
型號(hào): ADSP-21479KSWZ-2A
廠商: Analog Devices Inc
文件頁數(shù): 25/72頁
文件大小: 0K
描述: IC DSP SHARC 266MHZ LP 100LQFP
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: DAI,DPI,EBI/EMI,I²C,SPI,SPORT,UART/USART
時(shí)鐘速率: 266MHz
非易失內(nèi)存: ROM(4Mb)
芯片上RAM: 5Mb
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-LQFP-EP(14x14)
包裝: 托盤
其它名稱: Q6418433
Rev. A
|
Page 31 of 72
|
September 2011
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Table 28. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
tPCLK × 4
ns
tSTRIG
PCG Trigger Setup Before Falling Edge of PCG Input
Clock
4.5
ns
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input
Clock
3ns
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge Delay
After PCG Input Clock
2.5
12.5
ns
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
2.5 + (2.5 × tPCGIP)
12.5 + (2.5 × tPCGIP)ns
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
2.5 + ((2.5 + D – PH) × tPCGIP)
12.5 + ((2.5 + D – PH) × tPCGIP)ns
tPCGOW
1
Output Clock Period
2 × tPCGIP – 1
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-214xx SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1 Normal mode of operation.
Figure 17. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCK_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
tDTRIGCLK
tDPCGIO
tSTRIG
tHTRIG
tPCGOW
tDPCGIO
tPCGIP
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