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參數(shù)資料
| 型號： | ADS8517IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 948K |
| 代理商： | ADS8517IPWR |
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R/C
BUSY
MODE
Parallel
Data Bus
BYTE
t1
t3
t4
t1
t3
t6
t7
t5
t6
t8
t12
t11
t10
t12
t2
t9
t12
t9
t12
Previous
High Byte Valid
Hi-Z
Previous High
Byte Valid
Previous Low
Byte Valid
Not Valid
High Byte
Valid
Low Byte
Valid
Hi-Z
High Byte
Valid
Acquire
Convert
Acquire
Convert
t21
t9
t21
t9
Hi-Z State
High Byte
Hi-Z State
Low Byte
Hi-Z State
t4
t3
t1
R/C
BUSY
CS
Data Bus
BYTE
SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
Parallel Output (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N are available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
Figure 30. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High)
Figure 31. CS to Control Conversion and Read Timing With Parallel Outputs
16
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
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