參數(shù)資料
型號： ADS8517IPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28
封裝： GREEN, PLASTIC, TSSOP-28
文件頁數(shù)： 7/38頁
文件大?。?/td> 948K
代理商： ADS8517IPWR
READING DATA
Parallel Output
www.ti.com ................................................................................................................................................. SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009
The ADS8517 outputs serial or parallel data in straight binary (SB) or binary twos complement data output
format. If SB/BTC (pin 7) is high, the output is in SB format; if it is low, the output is in BTC format. Refer to
Table 4 for the ideal output codes. The first conversion immediately following a power-up does not produce a
valid conversion result.
The parallel output can be read without affecting the internal output registers; however, reading the data through
the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on the
parallel port before reading the same data on the serial port, but data cannot be read through the serial port
before reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output(1)
CS
R/C
BUSY
EXT/INT
DATACLK
OPERATION
↓
0
1
0
Output
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
0
↓
1
0
Output
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
↓
0
1
Input
Initiates conversion N. Internal clock still runs conversion process.
0
↓
1
Initiates conversion N. Internal clock still runs conversion process.
↓
1
Input
Conversion N completed. Valid data from conversion N clocked out on SDATA
synchronized to external data clock.
↓
1
0
1
Input
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
↑
0
1
Input
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
↑
X
Input
New conversion initiated without acquisition of a new signal. Data are invalid. CS and/or
R/C must be high when BUSY goes high.
X
0
X
New convert commands ignored. Conversion N in progress..
(1)
See Figure 34, Figure 35, and Figure 36 for constraints on data valid from conversion N–1.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
BINARY TWOS COMPLEMENT
(SB/BTC LOW)
STRAIGHT BINARY (SB/BTC HIGH)
DESCRIPTION
ANALOG INPUT
Full-scale range
±10
0 V to 5 V
0 V to 4 V
HEX
Least significant bit (LSB)
305
V
76
V
61
V
BINARY CODE
CODE
BINARY CODE
HEX CODE
+Full-scale (FS – 1LSB)
9.999695 V
4.999924 V
3.999939 V
0111 1111 1111 1111
7FFF
1111 1111 1111 1111
FFFF
Midscale
0 V
2.5 V
2 V
0000 0000 0000 0000
0000
1000 0000 0000 0000
8000
1 LSB below midscale
305
V
2.499924 V
1.999939 V
1111 1111 1111 1111
FFFF
0111 1111 1111 1111
7FFF
–Full-scale
-10 V
0 V
1000 0000 0000 0000
8000
0000 0000 0000 0000
0000
To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left
unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other
combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on
D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the eight most significant bits are valid with the MSB
on D7. When BYTE is high, the eight least significant bits are valid with the LSB on D0. BYTE can be toggled to
read both bytes within one conversion cycle.
Upon initial device power-up, the parallel output contains indeterminate data.
Copyright 2008–2009, Texas Instruments Incorporated
15
Product Folder Link(s): ADS8517
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