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參數(shù)資料
| 型號： | ADS8517IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 6/38頁 |
| 文件大?。?/td> | 948K |
| 代理商： | ADS8517IPWR |
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STARTING A CONVERSION
SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
The combination of CS (pin 23) and R/C (pin 22) held low for a minimum of 40 ns puts the sample-and-hold of
the ADS8517 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion N
completes and the internal output register has been updated. All new convert commands received while BUSY is
low are ignored.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5
s between convert
commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS,
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/INT Tied High)
CS
R/C
BUSY
OPERATION
1
X
None. Data bus is in High-Z state.
↓
0
1
Initiates conversion N. Data bus remains in High-Z state.
0
↓
1
Initiates conversion N. Data bus enters High-Z state.
0
1
↑
Conversion N completed. Valid data from conversion N on the data bus.
↓
1
Enables data bus with valid data from conversion N.
↓
1
0
Enables data bus with valid data from conversion N–1(1). Conversion N in progress.
0
↑
0
Enables data bus with valid data from conversion N–1(1). Conversion N in progress.
0
↑
New conversion initiated without acquisition of a new signal. Data are invalid. CS and/or R/C
must be high when BUSY goes high.
X
0
New convert commands ignored. Conversion N in progress.
(1)
CS and R/C are internally ORed and level-triggered. It does not matter which input goes low first when initiating a
conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical input is low at
least tsu2 ≥ 10 ns before the initiating input. If EXT/INT (pin 8) is low when initiating conversion N, serial data from
conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal Data Clock in the
Reading Data section for more information.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This
configuration has no effect when using the internal data clock in the serial output mode. However, when using an
active external data clock, the parallel and serial outputs are affected whenever R/C goes high; refer to the
Reading Data section for more information. In the internal clock mode, data are clocked out every convert cycle
regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to high.
Therefore, data always represent the previously-completed conversion, even when read during a conversion.
14
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
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