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| 型號： | ADS8517IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 22/38頁 |
| 文件大?。?/td> | 948K |
| 代理商： | ADS8517IPWR |
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ADS8517 AS AN SPI MASTER DEVICE (INT/EXT TIED LOW)
Microcontroller
SPISlave
CPOL=0(inactiveSCLKisLOW)
CPHA=0or1(datavalidoneitherSCLKedge)
NOTE:
ADS8517
SPIMaster
TOUT
SS
MOSI
SCLK
R/C
BUSY
SDATA
DATACLK
EXT/INT
CS
BYTE
www.ti.com ................................................................................................................................................. SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009
Figure 44 shows a simple interface between the ADS8517 and an SPI-equipped microcontroller or TMS320
series digital signal processor (DSP) when using the internal serial data clock. This interface assumes that the
microcontroller or DSP is configured as an SPI slave, is capable of receiving 16-bit transfers, and that the
ADS8517 is the only serial peripheral on the SPI bus.
Figure 44. ADS8517 as SPI Master
To maintain synchronization with the ADS8517, the microcontroller slave select (SS) input should be connected
to the BUSY output of the ADS8517. When a transition from high-to-low occurs on BUSY (indicating the current
conversion is in process), the ADS8517 internal SCLK begins shifting the previous conversion data into the
MOSI pin of the microcontroller. In this scenario, the CONV input to the ADS8517 can be controlled from an
external trigger source, or a trigger generated by the microcontroller. The ADS8517 internal SCLK provides 2 ns
(min) of setup time and 41 ns (min) of hold time on the SDATA output (see td5 and td6 in Table 6), allowing the
microcontroller to sample data on either the rising or falling edge of SCLK.
Copyright 2008–2009, Texas Instruments Incorporated
29
Product Folder Link(s): ADS8517
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