參數(shù)資料
型號(hào)： ADS8517IPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28
封裝： GREEN, PLASTIC, TSSOP-28
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 948K
代理商： ADS8517IPWR
TAG FEATURE
2
33
32
34
16
15
4
19
20
21
18
1
A00
D
Q
D
Q
D
Q
D
Q
B00
A15
B15
TAG(B)
DATA(A)
DATA(B)
DATACLK
Nth Conversion Data
B15
B14
B13
A15
B00
B01
A00
A14
A13
A12
A15
A14
A13
A00
A01
17
ADS8517A
ADS8517B
TAG
DATA
DATACLK
Processor
SCLK
GPIO
SDI
TAG(A)=0
R/C
(bothAandB)
BUSY
(bothAandB)
SYNC
(bothAandB)
External
DATACLK
DATA(B)
DATA(A)
CS
R/C
CS
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
3
SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
The TAG feature allows data from multiple ADS8517 converters to be read on a single serial line. The converters
are cascaded together using the DATA pins as outputs and the TAG pins as inputs, as illustrated in Figure 37.
The DATA pin of the last converter drives the processor serial data input. Data are then shifted through each
converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot
be used for this configuration.
The preferred timing uses the discontinuous, external data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the External Data Clock section). The sampling period
must be sufficiently long enough to allow all data words to be read before starting a new conversion.
Note that in Figure 37, the state of the DATA pin at the end of a READ cycle reflects the state of the TAG pin at
the start of the cycle for each converter. The ADS8517 works the same way when it is running in external or
internal clock mode. That is, the state of the TAG pin is shown on the DATA pin at the 17th clock after all 16 bits
have shifted out. However, it is only practical to use the TAG feature with the external clock mode when multiple
ADS8517s are daisy-chained, so that they are running at the same clock speed. For example, when two
converters (ADS8517A and ADS8517B) are cascaded together, the 17th external clock cycle brings the MSB
data of ADS8517A onto the DATA pin of ADS8517B.
Figure 37. Timing of TAG Feature With Single Conversion (Using External DATACLK)
22
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
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