
ADN8102
Rev. B | Page 5 of 36
TIMING SPECIFICATIONS
Table 2. I2C Timing Parameters
Parameter
Min
Max
Unit
Description
fSCL
0
400
kHz
SCL clock frequency
tHD:STA
0.6
Not applicable
μs
Hold time for a start condition
tSU:STA
0.6
Not applicable
μs
Setup time for a repeated start condition
tLOW
1.3
Not applicable
μs
Low period of the SCL clock
tHIGH
0.6
Not applicable
μs
High period of the SCL clock
tHD:DAT
0
Not applicable
μs
Data hold time
tSU:DAT
10
Not applicable
ns
Data setup time
tR
1
300
ns
Rise time for both SDA and SCL
tF
1
300
ns
Fall time for both SDA and SCL
tSU:STO
0.6
Not applicable
μs
Setup time for a stop condition
tBUF
1
Not applicable
ns
Bus free time between a stop and a start condition
CIO
5
7
pF
Capacitance for each I/O pin
tRESET
10
Not applicable
ns
07
06
0-
01
0
S
P
Sr
S
SDA
SCL
tF
tR
tF
tR
tBUF
tLOW
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
tHD:STA
Figure 2. I2C Timing Diagram
07
06
0-
1
03
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
30
35
40
45
50
VO
L
T
A
G
E
(
V)
TIME (ns)
tRESET
DVCC (V)
DVCC MAX LIMIT
DVCC MIN LIMIT
RESET
Figure 3. Reset Timing Diagram