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| 型號： | ADN8102ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER 4CH XSTREAM 64LFCSP |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 應(yīng)用： | 以太網(wǎng)控制器 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 3.3 V |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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ADN8102
Rev. B | Page 25 of 36
I2C CONTROL INTERFACE
SERIAL INTERFACE GENERAL FUNCTIONALITY
The ADN8102 register set is controlled through a 2-wire
I2C interface. The ADN8102 acts only as an I2C slave device.
Therefore, the I2C bus in the system needs to include an I2C
master to configure the ADN8102 and other I2C devices that
may be on the bus. Data transfers are controlled using the two
I2C wires: the SCL input clock pin and the SDA bidirectional
data pin.
The ADN8102 I2C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to toggle
only when the SDA line is stable, unless indicating a start,
repeated start, or stop condition.
I2C INTERFACE DATA TRANSFERS—DATA WRITE
To write data to the ADN8102 register set, a microcontroller, or
any other I2C master, needs to send the appropriate control signals
to the ADN8102 slave device. The steps that need to be completed
are listed as follows, where the signals are controlled by the I2C
master, unless otherwise specified. A diagram of the procedure
can be seen in Figure 42.
1.
Send a start condition (while holding the SCL line high,
pull the SDA line low).
2.
Send the ADN8102 part address (seven bits) whose upper
five bits are the static value 10010b and whose lower two
bits are controlled by the ADDR[1:0] input pins. This transfer
should be MSB first.
3.
Send the write indicator bit (0).
4.
Wait for the ADN8102 to acknowledge the request.
5.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6.
Wait for the ADN8102 to acknowledge the request.
7.
Send the data (eight bits) to be written to the register whose
address was set in Step 5. This transfer should be MSB first.
8.
Wait for the ADN8102 to acknowledge the request.
9a. Send a stop condition (while holding the SCL line high,
pull the SDA line high) and release control of the bus.
9b. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 in
this procedure to perform another write.
9c. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 2 of
the read procedure (in the I2C Interface Data Transfers—
Data Read section) to perform a read from another address.
9d. Send a repeated start condition (while holding the SCL line
high, pull the SDA line low) and continue with Step 8 of
the read procedure (in the I2C Interface Data Transfers—
Data Read section) to perform a read from the same
address set in Step 5.
Figure 42 shows the ADN8102 write process. The SCL signal is
shown along with a general write operation and a specific example.
In the example, Data 0x92 is written to Address 0x6D of an
ADN8102 part with a part address of 0x4B. The part address is
seven bits wide. The upper five bits of the ADN8102 are internally
set to 10010b. The lower two bits are controlled by the ADDR[1:0]
pins. In this example, the bits controlled by the ADDR[1:0] pins
are set to 11b. In Figure 42, the corresponding step number is
visible in the circle under the waveform. The SCL line is driven by
the I2C master and never by the ADN8102 slave. As for the SDA
line, the data in the shaded polygons is driven by the ADN8102,
whereas the data in the nonshaded polygons is driven by the I2C
master. The end phase case shown is that of Step 9a.
Note that the SDA line only changes when the SCL line is low,
except for the case of sending a start, stop, or repeated start
condition, Step 1 and Step 9 in this case.
1
SCL
SDA
GENERAL CASE
EXAMPLE
START
REGISTER ADDR
ACK
STOP
DATA
R/W
FIXED PART ADDR
ADDR
[1:0]
2
3
4
5
6
7
8
9a
0
70
60
-0
08
Figure 42. I2C Write Diagram
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| ADN8102ACPZ-R7 | 功能描述:IC EQUALIZER 4CH XSTREAM 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:XStream™ 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| ADN8102-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.75 Gbps Quad Bidirectional CX4 Equalizer |
| ADN8102XCPZ | 功能描述:Ethernet Controller Interface 制造商:analog devices inc. 系列:XStream?? 包裝:- 零件狀態(tài):上次購買時間 應(yīng)用:以太網(wǎng)控制器 接口:I2C 電壓 - 電源:1.8 ~ 3.3V 封裝/外殼:- 供應(yīng)商器件封裝:- 安裝類型:- 標準包裝:1 |
| ADN8810 | 制造商:Analog Devices 功能描述:- Bulk |
| ADN8810ACP | 制造商:Analog Devices 功能描述:Current Source 24-Pin LFCSP EP |
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