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| 型號： | ADN8102ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER 4CH XSTREAM 64LFCSP |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 應用： | 以太網(wǎng)控制器 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 3.3 V |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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ADN8102
Rev. B | Page 18 of 36
Table 8. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps)
EQ_A[1:0] and
EQ_B[1:0] Pins
IN_Ax/IN_Bx
Configuration,
EQ[2:0]
Cable Optimized
FR4 Optimized
EQBY
Boost (dB)
Typical CX4 Cable
Length (Meters)
Boost (dB)
Typical FR4 Trace
Length (Inches)
X1
1
1.5
< 2
1.5
< 5
0
10
2 to 6
3.5
5 to 10
1
0
12
8 to 10
3.9
10 to 15
1
2
0
14
12 to 14
4.25
15 to 20
3
0
17
16 to 18
4.5
20 to 25
4
0
19
20 to 22
4.75
25 to 30
2
5
0
20
24 to 26
5.0
30 to 35
6
0
21
28 to 30
5.3
35 to 40
3
7
0
22
30 to 32
5.5
35 to 40
1 X = Don’t care
Table 9. Receive Configuration and Equalization Registers
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
IN_A/IN_B
configuration
0x80, 0xA0
PNSWAP
EQBY
EN
EQ[2]
EQ[1]
EQ[0]
0x30
IN_A/IN_B
EQ1 control
0x83, 0xA3
EQ CTL SRC
EQ1[5]
EQ1[4]
EQ1[3]
EQ1[2]
EQ1[1]
EQ1[0]
0x00
IN_A/IN_B
EQ2 control
0x84, 0xA4
EQ2[5]
EQ2[4]
EQ2[3]
EQ2[2]
EQ2[1]
EQ2[0]
0x00
IN_Ax/IN_Bx
FR4 control
0x85, 0x8D, 0x95,
0x9D, 0xA5, 0xAD,
0xB5, 0xBD
LUT SELECT
LUT FR4/CX4
0x00
Loss of Signal/Signal Detect
An independent signal detect output is provided for all eight
input ports of the device. The signal-detect function measures
the low frequency amplitude of the signal at the receiver input
and compares this measurement with a defined threshold level.
If the measurement indicates that the input signal swing is
smaller than the threshold for 250 μs, the channel indicates a
loss-of-signal event. Assertion and deassertion of the LOS signal
occurs within 100 μs of the event.
The LOS-assert and LOS-deassert levels are set on a per channel
basis through the I2C control interface, by writing to the IN_A/
IN_B LOS threshold and IN_A/IN_B LOS hysteresis registers,
respectively. The recommended settings are IN_A/IN_B LOS
threshold = 0x0C and IN_A/IN_B LOS hysteresis = 0x0D.
All ports are factory tested with these settings to ensure that an
LOS event is asserted for single-ended dc input swings less than
20 mV and is deasserted for single-ended dc input swings greater
than 225 mV.
The LOS status for each individual channel can be accessed
through the I2C control interface. The independent channel
LOS status can be read from the IN_A/IN_B LOS status registers
(Address 0x1F and Address 0x3F). The four LSBs of each register
represent the current LOS status of each channel, with high
representing an ongoing LOS event. The four MSBs of each
register represent the historical LOS status of each channel,
with high representing a LOS event at any time on a specific
channel. The MSBs are sticky and remain high once asserted
until cleared by the user by overwriting the bits to 0.
Recommended LOS Settings
Recommended settings for LOS are as follows:
Set IN_A/IN_B LOS threshold to 0x0C for an assert
voltage of 20 mV differential (40 mV p-p differential).
Set IN_A/IN_B LOS hysteresis to 0x0D for a deassert voltage
of 225 mV differential (450 mV p-p differential).
LANE INVERSION
The input P/N inversion is a feature intended to allow the user
to implement the equivalent of a board-level crossover in a much
smaller area and without additional via impedance discontinuities
that degrade the high frequency integrity of the signal path. The
P/N inversion is available on a per port basis and is controlled
through the I2C control interface. The P/N inversion is accom-
plished by writing to the PNSWAP bit (Bit 6) of the IN_A/IN_B
configuration register (see Table 9) with low representing a
noninverting configuration and high representing an inverting
configuration. Note that using this feature to account for signal
inversions downstream of the receiver requires additional attention
when switching connectivity.
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| ADN8102ACPZ-R7 | 功能描述:IC EQUALIZER 4CH XSTREAM 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:XStream™ 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| ADN8102-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.75 Gbps Quad Bidirectional CX4 Equalizer |
| ADN8102XCPZ | 功能描述:Ethernet Controller Interface 制造商:analog devices inc. 系列:XStream?? 包裝:- 零件狀態(tài):上次購買時間 應用:以太網(wǎng)控制器 接口:I2C 電壓 - 電源:1.8 ~ 3.3V 封裝/外殼:- 供應商器件封裝:- 安裝類型:- 標準包裝:1 |
| ADN8810 | 制造商:Analog Devices 功能描述:- Bulk |
| ADN8810ACP | 制造商:Analog Devices 功能描述:Current Source 24-Pin LFCSP EP |
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