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參數資料
| 型號： | ADN2860ACPZ25-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 3CH 25K 24-LFCSP |
| 標準包裝： | 1 |
| 接片： | 128，512，512 |
| 電阻（歐姆）： | 25k |
| 電路數： | 3 |
| 溫度系數： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | ADN2860ACPZ25RLCT |
ADN2860
Rev. B | Page 15 of 20
THEORY OF OPERATION
The ADN2860 digital potentiometer operates as a true variable
resistor. The RDAC register contents determine the resistor
wiper position. The RDAC register acts like a scratchpad
register, allowing unlimited resistance setting changes. RDAC
register contents are changed using the ADN2860’s serial I2C
interface. See the RDAC I2C Interface section for the format of
the data words and commands to program the RDAC registers.
Each RDAC register has a corresponding EEPROM memory
location, which provides nonvolatile storage of resistor wiper
position settings. The ADN2860 provides commands to store
the RDAC register contents to their respective EEPROM
memory locations. During subsequent power-on sequences, the
RDAC registers are automatically loaded with the stored values.
Saving data from an RDAC register to EEPROM memory takes
approximately 25 ms and consumes 35 mA.
In addition to moving data between RDAC registers and
EEPROM memory, the ADN2860 provides other shortcut
commands.
Table 9. ADN2860 Shortcut Commands
No.
Function
1
2
3
Decrement RDAC 6 dB (shift data bits right)
4
Decrement all RDACs 6 dB (shift all data bits right)
5
Decrement RDAC one step
6
Decrement all RDACs one step
7
8
Increment RDAC 6 dB (shift data bits left)
9
Increment all RDACs 6 dB (shift all data bits left)
10
Increment RDAC one step
11
Increment all RDACs one step
__________________________
1 Command leaves the device in the EEPROM read power state. Issue the NOP
command to return the device to the idle state.
2 Command requires acknowledge polling after execution.
LINEAR INCREMENT AND DECREMENT
COMMANDS
The increment and decrement commands (Commands 10, 11,
5, and 6) are useful for linear step adjustment applications.
These commands simplify microcontroller software coding by
allowing the controller to send only an increment or decrement
command to the ADN2860. The adjustment can be directed to
an individual RDAC or to all three RDACs.
LOGARITHMIC TAPER MODE ADJUSTMENT
(
±6 dB/STEP)
The ADN2860 accommodates logarithmic taper adjustment of
the RDAC wiper position(s) by shifting the register contents
left/right for increment/decrement operations. Commands 8, 9,
3, and 4 are used to logarithmically increment or decrement the
wiper positions individually or change all three channel settings
at the same time.
Incrementing the wiper position by +6 dB doubles the RDAC
register value, whereas decrementing by 6 dB halves it.
Internally, the ADN2860 uses a shift register to shift the bits left
and right to achieve a logarithmic increment or decrement.
Nonideal ±6 dB step adjustment occurs under certain conditions.
Table 10 illustrates how the shifting function affects the data
bits of an individual RDAC. Each row going down the table
represents a successive shift operation. Note that the left-shift
commands (Commands 10 and 11) were modified such that if
the data in the RDAC register equals 0 and the data is shifted,
the RDAC register is set to Code 1. Similarly, if the data in the
RDAC register is greater than or equal to midscale and the data
is left shifted, the data in the RDAC register is automatically set
to full scale. This makes the left-shift function as close as possible
to a logarithmic adjustment.
The right-shift commands (Commands 3 and 4) are ideal only
if the LSB is a 0 (ideal logarithmic = no error). If the LSB is 1,
the right-shift function generates a linear half LSB error.
Table 10. RDAC Register Contents after
±6 dB Step Adjustments
Left Shift (+6 dB/Step)
Right Shift (6 dB/Step)
0 0000 0000
1 1111 1111
0 0000 0001
0 1111 1111
0 0000 0010
0 0111 1111
0 0000 0100
0 0011 1111
0 0000 1000
0 0001 1111
0 0001 0000
0 0000 1111
0 0010 0000
0 0000 0111
0 0100 0000
0 0000 0011
0 1000 0000
0 0000 0001
1 0000 0000
0 0000 0000
1 1111 1111
0 0000 0000
1 1111 1111
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift command (Commands 3 and 4) execution contains
an error only for odd numbers of bits. Even numbers of bits are
ideal. Figure 26 shows a plot of Log_Error, that is, 20 ×
Log10(error/code), for the ADN2860.
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| ADN2860-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Channel Digital Potentiometer with Nonvolatile Memory |
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| ADN2865ACP-RL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES |
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