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參數(shù)資料
型號: ADN2860ACPZ25-RL7
廠商: Analog Devices Inc
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: IC POT DGTL 3CH 25K 24-LFCSP
標準包裝: 1
接片: 128,512,512
電阻(歐姆): 25k
電路數(shù): 3
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V,±2.25 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 剪切帶 (CT)
其它名稱: ADN2860ACPZ25RLCT
ADN2860
Rev. B | Page 3 of 20
ELECTRICAL CHARACTERISTICS
Single supply: VDD = 2.7 V to 5.5 V and 40°C < TA < +85°C, unless otherwise noted.
Dual supply: VDD = +2.25 V or +2.75 V, VSS = 2.25 V or 2.75 V, and 40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Unit
DC CHARACTERISTICS,
RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, 7-bit channel
0.75
+0.75
LSB
RWB, 9-bit channels
2.5
+2.5
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, 7-bit channel
0.5
+0.5
LSB
R-INL
RWB, 9-bit channels, VDD = 5.5 V
2.0
+2.0
LSB
R-INL
RWB, 9-bit channels, VDD = 2.7 V
4.0
+4.0
LSB
Resistance Temperature Coefficent
(RWB/RWB)/T × 106
35
ppm/°C
Wiper Resistance
RW
VDD = 5 V, IW = 1 V/RWB
100
150
Ω
VDD = 3 V, IW = 1 V/RWB
250
400
Ω
Channel Resistance Matching
RAB1/RAB2
Ch 1 and Ch 2 RWB, Dx = 0x1FF
0.1
%
Nominal Resistor Tolerance
RAB/RAB
Dx = 0x3FF
15
+15
%
DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity3
DNL
7-bit channel
0.5
+0.5
LSB
DNL
9-bit channels
2.0
+2.0
LSB
Integral Nonlinearity3
INL
7-bit channel
0.5
+0.5
LSB
INL
9-bit channels
2.0
+2.0
LSB
Voltage Divider Temperature
Coefficent
(VW/VW)/T × 106
Code = half scale
15
ppm/°C
Full-Scale Error
VWFSE
7-bit channel/9-bit channels,
code = full scale
1/2.75
0/0
LSB
Zero-Scale Error
VWZSE
7-bit channel/9-bit channels,
code = zero scale
0/0
1/2.0
LSB
RESISTOR TERMINALS
Terminal Voltage Range4
VA, B, W
VSS
VDD
V
Capacitance5 Ax, Bx
CA,B
f = 1 kHz, measured to GND,
code = half scale
85
pF
Capacitance5 Wx
CW
f = 1 kHz, measured to GND,
code = half scale
95
pF
Common-Mode Leakage Current5, 6
ICM
VW = VDD/2
0.01
1
μA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
VDD = 5 V, VSS = 0 V
2.4
V
VDD/VSS = +2.7 V/0 V or
VDD/VSS = ±2.5 V
2.1
V
Input Logic Low
VIL
VDD = 5 V, VSS = 0 V
0.8
V
VDD/VSS = +2.7 V/0 V or
VDD/VSS = ±2.5 V
0.6
V
Output Logic High (SDA)
VOH
RPULL-UP = 2.2 kΩ to VDD = 5 V,
VSS = 0 V
4.9
V
Output Logic Low
VOL
RPULL-UP = 2.2 kΩ to VDD = 5 V,
VSS = 0 V
0.4
V
WP Leakage Current
I
WP
WP = VDD
9
μA
A0 Leakage Current
IA0
A0 = GND
3
μA
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