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參數(shù)資料
| 型號： | ADN2860ACPZ25-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 3CH 25K 24-LFCSP |
| 標準包裝： | 1 |
| 接片： | 128，512，512 |
| 電阻（歐姆）： | 25k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | ADN2860ACPZ25RLCT |
ADN2860
Rev. B | Page 4 of 20
Parameter
Symbol
Conditions
Min
Max
Unit
Input Leakage Current (Excluding WP
and A0)
II
VIN = 0 V or VDD
±1
μA
Input Capacitance5
CI
5
pF
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
2.7
5.5
V
Dual-Supply Power Range
VDD/VSS
±2.25
±2.75
V
Positive Supply Current
IDD
VIH = VDD or VIL = GND, VSS = 0 V
5
15
μA
Negative Supply Current
ISS
VIH = VDD or VIL = GND, VDD =
2.5 V, VSS = 2.5 V
5
15
μA
EEMEM Data Storing Mode Current
IDD_STORE
VIH = VDD or VIL = GND
35
mA
EEMEM Data Restoring Mode Current
IDD_RESTORE
VIH = VDD or VIL = GND
2.5
mA
Power Dissipation7
PDISS
VIH = VDD = 5 V or VIL = GND
25
75
μW
Power Supply Sensitivity5
PSS
VDD = 5 V ± 10%
0.01
0.025
%/%
1 Typical represents average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
03615-015
SDA
SCL
PS
SP
t1
t2
t3
t8
t9
t4
t5
t7
t10
t6
Figure 2. I2C Timing Diagram
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