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參數(shù)資料
| 型號： | ADN2860ACPZ25-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 3CH 25K 24-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 128，512，512 |
| 電阻（歐姆）： | 25k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | ADN2860ACPZ25RLCT |
ADN2860
Rev. B | Page 5 of 20
ELECTRICAL CHARACTERISTICS
Single Supply: VDD = 3 V to 5.5 V and 40°C < TA < +85°C, unless otherwise noted.
Dual Supply: VDD = +2.25 V or +2.75 V, VSS = 2.25 V or 2.75 V, and 40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Bandwidth 3 dB
BW
VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ.
125/12
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz.
0.05
%
VW Settling Time
tS
VA = VDD, VB = 0 V,
VW = 0.50% error band,
code = 0x000 to 0x100, RAB = 25 kΩ/250 kΩ.
4/36
μs
Resistor Noise Spectral Density
eN_WB
RAB = 25 kΩ/250 kΩ, TA = 25°C.
14/45
nV√Hz
Digital Crosstalk
CT
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change.
80
dB
Analog Crosstalk
CAT
Signal input at A0 and measure output
at W1, f = 1 kHz.
72
dB
INTERFACE TIMING CHARACTERISTICS (Apply
SCL Clock Frequency
fSCL
400
kHz
tBUF Bus Free Time between Stop and Start
t1
1.3
μs
tHD;STA Hold Time (Repeated Start)
t2
After this period, the first clock pulse is
generated.
600
ns
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
50
μs
tSU;STA Setup Time for Start Condition
t5
600
ns
tHD;DAT Data Hold Time
t6
900
ns
tSU;DAT Data Setup Time
t7
100
ns
tR Rise Time of Both SDA and SCL Signals
t8
300
ns
tF Fall Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for Stop Condition
t10
600
ns
EEMEM Data Storing Time
tEEMEM_STORE
26
ms
EEMEM Data Restoring Time at Power-On
tEEMEM_RESTORE1
360
μs
EEMEM Data Restoring Time on Restore
tEEMEM_RESTORE2
360
μs
Command or Reset Operation
EEMEM Data Rewritable Time
tEEMEM_REWRITE
540
μs
FLASH/EE MEMORY RELIABILITY
Endurance6
100
kcycles
Data Retention7
55°C.
100
years
1 Typical represents average readings at 25°C, VDD = 5 V.
2 All dynamic characteristics use VDD = 5 V.
3 Guaranteed by design and not subject to production test.
4 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
5 See Figure 2 for the location of measured values.
6 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at 40°C, +25°C, and +85°C. Typical endurance at 25°C is 700,000 cycles.
7 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature.
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