參數(shù)資料
型號： ADMC328
廠商： Analog Devices, Inc.
英文描述： 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達(dá)控制器)
中文描述： 28 - ROM的鉛基于DSP的電機(jī)控制器（28腳含光盤，數(shù)字信號處理的的馬達(dá)控制器）
文件頁數(shù)： 22/36頁
文件大小： 470K
代理商： ADMC328
ADMC328
–22–
REV. A
particular value written to the register is unimportant since
writing to WDT IMER simply reloads the first value written
to this register.
Programmable Digital Input/Output
T he ADMC 328 has 9 programmable digital input/output
(PIO) pins that are all multiplexed with other functions.
T he 9 PIO lines PIO0-PIO8 are multiplexed with the serial
port (pins PIO0/T FS1 to PIO5/RFS1), the CLK OUT (pin
PIO6/CLK OUT ) and the auxiliary PWM outputs (pins
POI7/AUX and PIO8/AUX 0). When configured as a PIO,
each of these 9 pins can act as an input, output, or an inter-
rupt source.
T he operating mode of pins PIO0/T FS1 to PIO7/AUX 1 is
controlled by the PIOSELECT register. T his 8-bit register
has a bit for each input so that the mode of each pin may be
selected individually. Bit 0 of PIOSELECT controls the
operation of the PIO0/T FS1 pin. Bit 1 controls the PIO1/
DT 1 pin, etc. Setting the appropriate bit in the
PIOSELECT register causes the corresponding pin to be
configured for PIO functionality. Clearing the bit selects
the alternate (SPORT , CLK OUT , or AUX PWM) mode of
the corresponding pin. Following power-on reset, all bits of
PIOSELECT are set such that PIO functionality is se-
lected. T he operating mode of the PIO8/AUX 0 pin is se-
lected by bit 1 of the PIODAT A1 register. In a manner
identical to the PIOSELECT register, setting this bit en-
ables PIO functionality (PIO8) while clearing the bit en-
ables auxiliary PWM functionality (AUX 0).
Once PIO functionality has been selected for any or all of
these 9 pins, the direction may be set by the 8-bit
PIODIR0 register (for PIO0-PIO7) and the 1-bit PIODIR1
register (for PIO8). Clearing any bit configures the corre-
sponding PIO line as an input while setting the bit config-
ures it as an output. By default following power-on or reset
all bits of PIODIR0 and PIODIR1 are cleared configuring
PIO lines as inputs.
T he data of the PIO0 to PIO8 lines is controlled by the
PIODAT A0 register (for PIO0 to PIO7) and bit 0 of the
PIODAT A1 register (for PIO8). T hese registers can be
used to read data from those PIO lines configured as inputs
and write data to those configured as outputs. Any of the 9
pins (PIO0/T FS1 to PIO8/AUX 0) that have been config-
ured for PIO functionality can be made to act as an inter-
rupt source by setting the appropriate bit of he
PIOINT EN0 register (for PIO0 to PIO7) or the
PIOINT EN1 register (for PIO8). In order to act as an
interrupt source the pin must also be configured as an in-
put. An interrupt is generated upon a change of state (low-
to-high transition or high-to-low transition) on any input
that has been configured as an interrupt source. Following
a change of state event on any such input, the correspond-
ing bit is set in the PIOFLAG0 register (for PIO0 to PIO7)
and PIOFLAG1 (for PIO8) and a common PIO interrupt
is generated. Reading the PIOFLAG0 and PIOFLAG1
registers permits determining the interrupt source. Reading
the PIOFLAG0 and PIOFLAG1 registers automatically
clears all bits of the registers. Following power-on or reset,
all bits of PIOINT EN0 and PIOINT EN1 are cleared so
that no interrupts are enabled.
Each PIO line has an internal pull-down resistor so that
following power-on or reset all 9 lines are configured as
input PIOs and will be read as logic lows if left uncon-
nected.
PIO Registers
shown at the end of the data sheet.
Interrupt Control
T he ADMC328 can respond to 8 different interrupt
sources, some of which are generated by internal DSP core
interrupts and others from the motor control peripherals.
T he DSP core interrupts include the following:
·
·
·
·
transmit (or
IRQ1
) interrupt
·
T wo software interrupts
·
An interval timer time out interrupt
Reserved
Power up (or
RESET
) interrupt
A peripheral (or
IRQ2)
interrupt
A SPORT 1 receive (or
IRQ0
) and a SPORT 1
In addition, the motor control peripherals add other inter-
rupts that include:
·
·
·
A PWMSYNC interrupt
A programmable input/output (PIO) interrupt
A PWM trip interrupt
T he core interrupts are internally prioritized and individu-
ally maskable. All peripheral interrupts are multiplexed into
the DSP core through the peripheral (
IRQ2
) interrupt
.
T he PWMSYNC interrupt is triggered by a low-to-high
transition on the PWMSYNC pulse. T he
PWMTRIP
inter-
rupt is triggered on a high-to-low transition on the
PW-
MTRIP
pin, an over current on the I
SENSE
pin, or by
writing to the PWMSWT register. A PIO interrupt is de-
tected on any change of state (high-to-low or low-to-high)
on the PIO lines.
T he ADMC328 interrupt control system is configured and
controlled by the IFC, IMASK and ICNT L registers of the
DSP core and by the IRQFLAG register for the
PWMSYNC and PWMT RIP interrupts. PIO interrupts are
enabled and disabled by the PIOENT 0 and PIOINT 1
registers.
Table IX. Interrupt vector addresses
Interrupt Source
Interrupt Vector
Address
0x0000 (Reserved)
0x002C (Highest Priority)
0x0004
0x000C
0x0008
0x0018
0x001C
0x0020
0x0024
0x0028 (Lowest Priority)
Reset
PWMTRIP
Peripheral Interrupt (
IRQ2
)
PWMSY NC
PIO
Software Interrupt 1
Software Interrupt 0
SPORT 1 T ransmit Interrupt or
IRQ1
SPORT 1 Receive Interrupt or
IRQ0
T imer
Interrupt Masking
Interrupt masking (or disabling) is controlled by the
IMASK register of the DSP core. T his register contains
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