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參數(shù)資料
| 型號： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機控制器（28腳含光盤，數(shù)字信號處理的的馬達控制器） |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 470K |
| 代理商： | ADMC328 |
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ADMC328
–16–
REV. A
define the on-times in both the first and second halves of
the PWM period. As a result, it is possible to adjust the on-
time over the whole period in increments of t
. T his corre-
sponds to an effective PWM resolution of t
in double
update mode (or 50 ns for a 20 MHz CLK OUT ).
T he achievable PWM switching frequency at a given PWM
resolution is tabulated in T able V.
Table V. Achievable PWM resolution in single and
double update modes
Resolution Single update mode
(Bit)
PWM frequency (kHz) PWM frequency (kHz)
Double update mode
8
9
39.1
19.5
9.8
4.9
2.4
78.1
39.1
19.5
9.8
4.9
10
11
12
Minimum Pulsewidth: PWMPD Register
In many power converter switching applications, it is desir-
able to eliminate PWM switching signals below a certain
width. It takes a finite time to both turn on and turn off
modern power semiconductor devices. T herefore, if the
width of any of the PWM signals goes below some mini-
mum value, it may be desirable to completely eliminate the
PWM switching for that particular cycle.
T he allowable minimum on-time for any of the six PWM
outputs over half a PWM period that can be produced by
the PWM controller may be programmed using the
PWMPD register. T he minimum on-time is programmed
in increments of t
so that the minimum on-time that will
be produced over any half PWM period, T
min
, is related to
the value in the PWMPD register by:
T
min
= PWMPD
3
t
CK
so that a PWMPD value of 0x002 defines a permissible
minimum on-time of 100 ns for a 20MHz CLK OUT .
In each half cycle of the PWM, the timing unit checks the
on-time of each of the six PWM signals. If any of the times
is found to be less than the value specified by the PWMPD
register, the corresponding PWM signal is turned OFF for
the entire half period and its complementary signal is
turned completely ON.
C onsider the example where PWMT M = 200,
PWMC HA =5, PWMDT = 3, and PWMPD = 10 with a
C L K OUT of 20 MHz while operating in single update
mode. For this case, the PWM switching frequency is 50
kHz and the dead time is 300 ns. T he minimum permis-
sible on-time of any PWM signal over one-half of any pe-
riod is 500 ns. Clearly, for this example, the dead-time
adjusted on-time of the AH signal for one-half a PWM
period is (5-3)
3
50 ns = 100 ns. Because this is less than
the minimum permissible value, output AH of the timing
unit will remain OFF (0% duty cycle). Additionally, the
AL signal will be turned ON for the entire half period
(100% duty cycle).
Output Control Unit: PWMSEG Register
T he operation of the output control unit is managed by the
9-bit read/write PWMSEG register. T his register sets two
distinct features of the output control unit that are directly
useful in the control of ECM or BDCM.
T he PWMSEG register contains three crossover bits, one
for each pair of PWM outputs. Setting bit 8 of the
PWMSEG register enables the crossover mode for the AH/
AL pair of PWM signals; setting bit 7 enables crossover on
the BH/BL pair of PWM signals; and setting bit 6 enables
crossover on the CH/CL pair of PWM signals. If crossover
mode is enabled for any pair of PWM signals, the high-side
PWM signal from the timing unit (for example AH) is di-
verted to the associated low-side output of the output con-
trol unit so that the signal will ultimately appear at the AL
pin. Of course, the corresponding low-side output of the
timing unit is also diverted to the complementary high-side
output of the output control unit so that the signal appears
at pin AH. Following a reset, the three crossover bits are
cleared so that the crossover mode is disabled on all three
pairs of PWM signals.
T he PWMSEG register also contains six bits (bits 0 to 5)
that can be used to individually enable or disable each of
the six PWM outputs. If the associated bit of the
PWMSEG register is set, then the corresponding PWM
output is disabled irrespective of the value of the corre-
sponding duty cycle register. T his PWM output signal will
remain in the OFF state as long as the corresponding en-
able/disable bit of the PWMSEG register is set. T he PWM
output enable function is located after the crossover func-
tion. T hus, after a reset, all six enable bits of the
PWMSEG register are cleared so that all PWM outputs are
enabled by default.
In a manner identical to the duty cycle registers, the
PWMSEG is latched on the rising edge of the PWMSYNC
signal so that changes to this register only become effective
at the start of each PWM cycle in single update mode. In
double update mode, the PWMSEG register can also be
updated at the mid-point of the PWM cycle.
In the control of an ECM, only two inverter legs are
switched at any time, and often the high-side device in one
leg must be switched ON at the same time as the low-side
driver in a second leg. T herefore, by programming identi-
cal duty cycles for two PWM channels (for example, let
PWMCHA = PWMCHB) and setting bit 7 of the
PWMSEG register to crossover the BH/BL pair of PWM
signals, it is possible to turn ON the high-side switch of
phase A and the low-side switch of phase B at the same
time. In the control of an ECM, one inverter leg (phase C
in this example) is disabled for a number of PWM cycles.
T his disable may be implemented by disabling both the CH
and CL PWM outputs by setting bits 0 and 1 of the
PWMSEG register. T his is illustrated in Figure 9 where it
can be seen that both the AH and BL signals are identical,
because PWMCHA = PWMCHB, and the crossover bit for
phase B is set. In addition, the other four signals (AL, BH,
CH and CL) have been disabled by setting the appropriate
enable/disable bits of the PWMSEG register. For the situa-
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