![](http://datasheet.mmic.net.cn/310000/ADMC328_datasheet_16242419/ADMC328_14.png)
ADMC328
–14–
REV. A
with the A/D converter system. T he width of this
PWMSY NC pulse is programmable by the PWMSY NCWT
register. T he width of the PWMSY NC pulse, T
PWMSY NC
, is
given by:
(
T
t
PWMSYNCWT 1
PWMSYNC
CK
)
=
×
which means the width of the pulse is programmable from t
CK
to 256t
(corresponding to 50ns to 12.5
μ
s for a CLK OUT
rate of 20 MHz). Following a reset, the PWMSY NCWT
register contains 0x27 ( = 39) so that the default PWMSYNC
width is 2.0
μ
s.
PWM Duty Cycles: PWMCHA, PWMCHB, PWMCHC
Registers
T he duty cycles of the six PWM output signals are controlled
by the three duty cycle registers, PWMCHA, PWMCHB and
PWMCHC. T he integer value in the register PWMCHA
controls the duty cycle of the signals on AH and AL.
PWMCHB control the duty cycle of the signals on BH and
BL, and PWMCHC controls the duty cycle of the signals on
CH and CL. T he duty cycle registers are programmed in
integer counts of the fundamental time unit, t
, and define
the desired on-time of the high-side PWM signal produced by
the three-phase timing unit over half the PWM period. T he
switching signals produced by the three-phase timing unit are
also adjusted to incorporate the programmed dead time value
in the PWMDT register.
T he PWM is center based, resulting in the symmetrical out-
put waveforms about the center of the PWMSYNC period
(single update mode). Figure 7 presents a typical PWM tim-
ing diagram illustrating the PWM related registers
PWMCHA, PWMT M, PWMDT , and PWMSY NCWT con-
trol over the waveform timing in both half cycles of the PWM
period. T he magnitude of each parameter in the timing dia-
gram is determined by multiplying the integer value in each
register by t
CK
(typically 50 ns). It may be seen in the timing
diagram how dead time is incorporated into the waveforms by
moving the switching edges away from the instants set by the
PWMCHA register.
Each switching edge is moved by an equal amount (PWMDT
3
t
CK
) to preserve the symmetrical output patterns. T he
PWMSY NC pulse whose width is set by the PWMSY NCWT
register is also shown. Bit 3 of the SY ST AT register shows
which half cycle is active. T his can be useful in double update
mode as will be discussed later.
PWMCHA
2
3
PWMDT
PWMSYNCWT + 1
PWMCHA
PWMTM
PWMTM
AH
AL
PWMSYNC
SYSSTAT (3)
2
3
PWMDT
Figure 7. Typical PWM outputs of three-phase timing
unit in single update mode (active LO waveforms)
Figure 6. Overview of the PWM Controller of the ADMC328
PW MTM (15...0)
PW MDT (9...0)
PW MPD (15...0)
PW MSYNCW T (7...0)
MODECTRL (6)
PW MSEG(8...0)
OUTPUT
CONTROL
UNIT
GATE
DRIVE
UNIT
CLK
AH
AL
BH
BL
CH
CL
PW MTRIP
PW M DUTY CYCLE
REGISTERS
PW M CONFIGURATION
REGISTERS
PW MTRIP
TO INTERRUPT
CONTROLLER
OR
THREE-PHASE
PW M TIMING
UNIT
CLK
RESET
PW MSW T (0)
PW MCHA (15...0)
PW MCHB (15...0)
PW MCHC (15...0)
SYNC
SYNC
PW MSYNC
Over
Current
Trip
PW M Shutdown Controller
Analog Block
PW MGATE(9...0)
I
SENSE