參數(shù)資料
型號(hào)： ADMC328
廠商： Analog Devices, Inc.
英文描述： 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號(hào)處理的的馬達(dá)控制器)
中文描述： 28 - ROM的鉛基于DSP的電機(jī)控制器（28腳含光盤，數(shù)字信號(hào)處理的的馬達(dá)控制器）
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 470K
代理商： ADMC328
PRELIMINARY TECHNICAL DATA ADMC328
–13–
REV. A
f
C L K OU T
2
f
PW M
=
f
C L K IN
f
PW M
PW M T M =
×
T herefore, the PWM switching period, T
S
, can be written
as:
T
S
= 2
3
PWMT M
3
t
CK
For example, for a 20 MHz CLK OUT and a desired PWM
switching frequency of 10 kHz (T
S
= 100 μs), the correct
value to load into the PWMT M register is:
PW M T M
=
×
=
20
10
2 10 10
1000
6
3
=
0X 3E 8
T he largest value that can be written to the 16-bit PWMT M
register is 0xFFFF = 65,535 which corresponds to a mini-
mum PWM sw
itching frequency of:
f
20 10
2
65,535
×
153Hz
PWM,min
6
=
=
for a CLK OUT frequency of 20 MHz.
PWM Switching Dead Time: PWMDT Register
T he second important PWM block parameter that must be
initialized is the switching dead time. T his is a short delay
time introduced between turning off one PWM signal (for
example AH) and turning on its complementary signal, AL.
T his short time delay is introduced to permit the power
switch being turned off to completely recover its blocking
capability before the complementary switch is turned on. T his
time delay prevents a potentially destructive short-circuit
condition from developing across the dc link capacitor of a
typical voltage source inverter.
Dead time is controlled by the PWMDT register. T he dead
time is inserted into the three pairs of PWM output signals. T he
dead time, T
d
, is related to the value in the PWMDT register by:
PW M D T
f
C L K O U T
= 2
X
d
=
PW M D T
x 2 x
t
ck
T
T herefore, a PWMDT value of 0x00A (= 10), introduces a
1
μ
s delay between the turn off on any PWM signal (for ex-
ample AH) and the turn on of its complementary signal (AL).
T he amount of the dead time can therefore be programmed
in increments of 2t
(or 100 ns for a 20 MHz CLK OUT ).
T he PWMDT register is a 10-bit register so that its maximum
value is 0x3FF (= 1023) corresponding to a maximum pro-
grammed dead time of:
T d,max = 1023
x
2
x
t
C K
= 1023
x
2
x
50
x
10
= 102
μ
s
-9
for a CLK OUT rate of 20 MHz. Obviously, the dead time
can be programmed to be zero by writing 0 to the PWMDT
register.
PWM Operating Mode: MODECTRL and SYSSTAT
Registers
T he PWM controller of the ADMC328 can operate in two
distinct modes: single update mode and double update mode.
T he operating mode of the PWM controller is determined by
the state of bit 6 of the MODECT RL register. If this bit is
cleared the PWM operates in the single update mode. Setting
bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power on, bit 6 of the
MODECT RL register is cleared so that the default operating
mode is single update mode.
In single update mode, a single PWMSY NC pulse is pro-
duced in each PWM period. T he rising edge of this signal
marks the start of a new PWM cycle and is used to latch new
values from the PWM configuration registers (PWMT M,
PWMDT , PWMPD and PWMSY NCWT ) and the PWM
duty cycle registers (PWMCHA, PWMCHB and PWMCHC)
into the three-phase timing unit. In addition, the PWMSEG
register is also latched into the output control unit on the
rising edge of the PWMSY NC pulse. In effect, this means
that the parameters of the PWM signals can be updated only
once per PWM period at the start of each cycle. T hus, thre
generated PWM patterns are symmetrical about the mid-point
of the switching period.
In double update mode, there is an additional PWMSY NC
pulse produced at the mid-point of each PWM period. T he
rising edge of this new PWMSY NC pulse is again used to
latch new values of the PWM configuration registers, duty
cycle registers and the PWMSEG register. As a result it is
possible to alter both the characteristics (switching frequency,
dead time, minimum pulse width and PWMSY NC
pulsewidth) as well as the output duty cycles at the mid-point
of each PWM cycle. Consequently, it is possible to produce
PWM switching patterns that are no longer symmetrical about
the mid-point of the period (asymmetrical PWM patterns).
In the double update mode, operation in the first half or the
second half of the PWM cycle is indicated by bit 3 of the
SY SST AT register. In doubel update mode, this bit is cleared
during operation in the first half of each PWM period (be-
tween the rising edge of the original PWMSY NC pulse and
the rising edge of the new PWMSY NC pulse which is intro-
duced in double update mode). Bit 3 of the SY SST AT regis-
ter is set during the second half of each PWM period. If
required, a user may determine the status of this bit during a
PWMSYNC interrupt service routine.
T he advantages of the double update mode are that lower
harmonic voltages can be produced by the PWM process and
faster control bandwidths are possible. However, for a given
PWM switching frequency, the PWMSYNC pulses occur at
twice the rate in the double update mode. Because new duty
cycle values must be computed in each PWMSYNC interrupt
service routine, there is a larger computational burden on the
DSP in the double update mode.
Width of the PWMSYNC Pulse: PWMSYNCWT Register
T he PWM controller of the ADMC328 produces an internal
PWM synchronization pulse at a rate equal to the PWM
switching frequency in single update mode and at twice the
PWM frequency in the double update mode. T his
PWMSY NC synchronizes the operation of the PWM unit
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