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參數(shù)資料
| 型號： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達(dá)控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機(jī)控制器（28腳含光盤，數(shù)字信號處理的的馬達(dá)控制器） |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ADMC328 |
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PRELIMINARY TECHNICAL DATA ADMC328
–11–
REV. A
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the
ADMC328 with an external crystal.
ADMC328
XTAL
CLKIN
10 MHz
CLKOUT
RESET
Figure 4. Basic system configuration
Clock Signals
T he ADMC328 can be clocked by either a crystal or a
T T L-compatible clock signal. For normal operation, the
CLK IN input cannot be halted, changed during operation
nor operated below the specified minimum frequency. If
an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is
connected to the CLK IN pin of the ADMC328. In this
mode, with an external clock signal, the X T AL pin must be
left unconnected. T he ADMC328 uses an input clock with
a frequency equal to half the instruction rate; a 10 MHz
input clock yields a 50 ns processor cycle (which is equiva-
lent to 20 MHz). Normally, instructions are executed in a
single processor cycle. All device timing is relative to the
internal instruction rate, which is indicated by the
CLK OUT signal, when selected.
Because the ADMC328 includes an on-chip oscillator
feedback circuit, an external crystal may be used instead of
a clock source, as shown in Figure 4. T he crystal should
be connected across the CLK IN and X T AL pins, with two
capacitors as shown in Figure 4. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal
should be used. A clock output signal (CLK OUT ) is
generated by the processor at the processor’s cycle rate of
twice the input frequency.
Reset
T he AMDC328 DSP core and peripherals must be cor-
rectly reset when the device is powered up to assure proper
initialization. T he AMDC328 contains an integrated
power-on reset (POR) circuit which provides a complete
system reset on power-up and power-down. T he POR
circuit monitors the voltage on the ADMC328 V
DD
pin and
holds the DSP core and peripherals in reset while V
DD
is
less than the threshold voltage level, V
RST
. When this volt-
age is exceeded, the ADMC328 is held in reset for an addi-
tional 2
16
DSP clock cycles (t
RST
in Figure 5). On
power-down, when the voltage on the V
DD
pin falls below
V
RST
2
V
HYST
, the ADMC328 will be reset. Also, if the
external
RESET
pin is actively pulled low at any time after
power up, a complete hardware reset of the ADMC328 is
initiated.
VRST
VDD
RESET
VRST - VHYST
Figure 5. Power on reset operation
T he ADMC328 reset sets all internal stack pointers to the
empty stack condition, masks all interrupts, clears the
MST AT register and performs a full reset of all of the mo-
tor control peripherals. Following a power-up, it is possible
to initiate a DSP core and motor control peripheral reset by
pulling the
RESET
pin low. T he
RESET
signal must meet
the minimum pulse width specification, t
RST
. Following the
reset sequence, the DSP core starts executing code from
the internal PM ROM located at 0x0800.
DSP Control Registers
T he DSP core has a system control register, SYSCNT L,
memory mapped at DM (0x3FFF). SPORT 1 is configured
as a serial port when Bit 10 is set, or as flags and interrupt
lines when this bit is cleared. For proper operation of the
ADMC328, all other bits in this register must be cleared
(which is their default).
T he DSP core has a wait state control register,
MEMWAIT , memory mapped at DM (0x3FFE). For
proper operation of the ADMC328, this register must al-
ways contain the value 0x8000 (which is the default).
T he configuration of both the SYSCNT L and MEMWAIT
registers of the ADMC328 is shown at the end of the data
sheet.
THREE-PHASE PWM CONTROLLER
Overview
T he PWM generator block of the ADMC328 is a flexible,
programmable, three-phase PWM waveform generator that
can be programmed to generate the required switching
patterns to drive a three-phase voltage source inverter for
ac induction (ACIM), or permanent magnet synchronous
(PMSM) motors. In addition, the PWM block contains
special functions that considerably simplify the generation
of the required PWM switching patterns for control of the
electronically commutated motor (EC M) or brushless dc
motor (BDCM).
T he PWM generator produces three pairs of PWM signals
on the six PWM output pins (AH, AL, BH, BL, CH and
CL). T he six PWM output signals consist of three high side
drive signals (AH, BH and CH) and three low side drive
signals (AL, BL and CL ). T he generated PWM signals
are active HI PWM patterns. T he switching frequency,
dead time and minimum pulsewidths of the generated
PWM patterns are programmable using respectively the
PWMT M, PWMDT and PWMPD registers. In addition,
three registers (PWMCHA, PWMCHB and PWMCHC)
control the duty cycles of the three pairs of PWM signals.
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| ADMC401 | Single-Chip, DSP-Based High Performance Motor Controller |
| ADMC401-ADVEVALKIT | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-5 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADMC328TN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TN-XXX-YY | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328TR-XXX-YY | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328YN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
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